ESREF'2001, "12th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis", Arcachon, France , 1-5 octobre 2001.
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Titre : ESREF'2001, 12th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Arcachon, France , 1-5 octobre 2001.

Cité dans : [CONF016] ESREF, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis et Microelectronics and Reliability, décembre 2005.
Cité dans :[REVUE279] Elsevier Science, Microelectronics Reliability, Volume 41, Issues 9-10, Pages 1273-1736, September - October 2001.
Cité dans : [DATA224] Liste alphabétique des conférences, août 2016.
Cité dans : [DIV003]  Liste des actes de congrès par années, février 2003.
Cité dans : [DATA197] Les revues Microelectronics Reliability et Microelectronics Journal, ELSEVIER, décembre 2004.
Cité dans :[99DIV081] Dates des congrès sur les Convertisseurs Statiques, avril 2013.

Résumé : 14 mars 2001 (résumé de 3 pages).
Notification : 20 mai 2001
Final_Paper : 20 juin 2001
Date : 1-5 octobre 2001
Stockage : Thierry LEQUEU - LMP + tutorials
Lien : ESREF/2001/default.htm - le 5 octobre 2001.
Web : http://www.ixl.u-bordeaux.fr/

Vers : Tutorial T1 - Reliability Simulation for DSM full-chip Integrated Circuits
Vers : Tutorial T2 - From 0.18µm to 0.10µm Technology: A Blend of Evolution and Revolution
Vers : Tutorial T3 - Scanning Probe Microscopy Techniques for Failure Analysis of Microelectronic Devices - Fundamentals and Applications
Vers : Tutorial T4 - Reliability improvements in passive components
Vers : Auteurs connus
Vers : Liste des articles pertinents


Tutorial T1 - Reliability Simulation for DSM full-chip Integrated Circuits

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Chairman : A. Mouthaan (University of Twente - The Netherlands)
Lifeng Wu, Zhihong Liu (Celestry Design Technologies - USA)
As the transistor channel length scales down toward 0.1 micron and new processes loom ahead, circuit reliability simulation technologies should be on the finger-tips of the circuit designers to maximize design performance by minimizing design guard-band, to speed-up timing closure by reducing design iterations and to ensure long-term circuit reliability. Most common circuit reliability issues such as hot-carrier effect and electromigration are discussed in this tutorial as an alternative to TD fix of those issues. It has been shown that although the simulation flow has no obvious change in VDSM era and for new processes such as SOI, thin dielectric film and copper interconnect, more degradation mechanisms need to be investigated and more modeling issues need to be solved in the simulation procedure. Both full-chip transistor-level and cell-based solutions should be provided for circuit designers with million-transistor/million-gate capacity and Spice-accuracy. Reliability simulation constitutes one of the key roles in the full-chip design silicon-accuracy sign-off flow, as well as the parasitic extraction, coupling noise timing analysis and power grid IR drop.


Tutorial T2 - From 0.18µm to 0.10µm Technology: A Blend of Evolution and Revolution

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Chairman : O. Bonnaud (University of Rennes - France)
Fabio Pintchovsky (MOTOROLA - USA)
The semiconductor industry is unique in having sustained such rapid technology development over so long a period. This has enabled the industry to provide electronic products with substantially lower cost per function as well as higher performance each year. In this talk entitled "From 0.18µ to 0.10µ Technology: A Blend of Evolution and Revolution", integrated circuit technology characteristics required to maintain the historical rate of performance and cost improvements will be discussed. Those will include the areas of transistor engineering, oxide scaling, advanced interconnect systems and reliability.


Tutorial T3 - Scanning Probe Microscopy Techniques for Failure Analysis of Microelectronic Devices - Fundamentals and Applications

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Chairman : L.J. Balk (University of Wuppertal - Germany)
W. Mertin, E. Kubalek (Gerhard-Mercator-Universität Duisburg - Germany)
While the original applications of scanning probe microscopy (SPM) concentrated on nano scale surface investigation, a variety of applications suitable for the study of semiconductor properties and IC operation, and for IC failure localization has been developed in the last few years. The tutorial will start with reviewing the basic principles of SPM techniques and their corresponding equipment. Then it will demonstrate several advanced applications in the field which are of current interest in failure analysis of microelectronic devices, e.g. scanning capacitance microscopy, scanning thermal microscopy, scanning probe voltage and scanning probe current measurements.


Tutorial T4 - Reliability improvements in passive components

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Chairman : P. Leblanc (ASTRIUM - France)
P.O. Fagerholt (CLR Consult -Sweden)
A number of different measures taken on actual components can remarkably improve their reliability in operation. Such actions described are derating of:
- working dc voltage (remarkable example with solid tantalums),
- temperature by choosing styles with low ESR (solid Ta),
- maximum manufactured values (film resistors, ceramic chip capacitors),
- different wiper current accommodations in wire wound and non-wire wound potentiometers,
- exemplified burn in treatments, on solid Ta, NTC thermistors and film capacitors,
- choosing right designs (film capacitors subjected to high voltage rise times),
- precautions concerning wet aluminium electrolytics subjected to halogenated washing agents, and short power pulses applied on metal oxide resistors with films on glass rods,
- some application precautions (NTC and PTC thermistors, ceramic class 2 capacitors).


Auteurs connus

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TOPIC_2 : Bonnaud 1325 / 1331 / 1335
TOPIC_2 : J.F. Llibre

TOPIC_3 : Pogany - Vienne 1385
TOPIC_3 : J.P. Chante 1433
TOPIC_3 : Claeys 1443
TOPIC_3 : Ciappa 1459

TOPIC_4 : Touboul 1471 + Testing Interface 1495
TOPIC_4 : Pogany 1501
TOPIC_4 : Fouillat 1513

TOPIC_6 : Thermal resistance 1591
TOPIC_6 : Claeys 1597

TOPIC_7 : 3D voids métalization simulation 1626

TOPIC_8 : Bosc 1671
TOPIC_8 : Coquery 1695
TOPIC_8 : EDF pour thyristors reliability 1701
TOPIC_8 : Bonnaud 1707
TOPIC_8 : Power cycling module 1713
TOPIC_8 : Zardini 1731


Liste des articles pertinents

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  [1] :  [PAP375]  A. MUEHLHOFF, An extrapolation model for lifetime prediction for off-state -degradation of MOS-FETs, ESREF'2001, pp. 1289-1293.
  [2] :  [PAP376]  F. MONSIEUR, E. VINCENT, D. ROY, S. BRUYERE, G.PANANAKAKIS, G. GHIBAUDO, Determination of dielectric breakdown Weibull distribution parameters confidence bounds for accurate ultrathin oxide reliability predictions, ESREF'2001, pp. 1295-1300.
  [3] :  [PAP363]  P.O. Fagerholt , Reliability improvements in passive components, ESREF'2001, pp. 1279-1288.
  [4] :  [PAP364]  H. Toutah, J.F. Llibre, B. Tata-Ighil, T. Mohammed-Brahim, Y. Helen, G. Gautier, O. Bonnaud, Improved stability of large area excimer laser crystallised polysilicon thin film transistors under DC and AC operating, ESREF'2001, pp. 1325-1329
  [5] :  [PAP365]  M. Litzenberger, R. Pichler, S. Bychikhin, D. Pogany, K. Esmak, H. Gossner, E. Gornik, Effect of pulse risetime on trigger homogeneity in single finger grounded gate nMOSFET electrostatic discharge protection devices, ESREF'2001, pp. 1385-1390
  [6] :  [PAP366]  D. Lewis, V. Pouget, T. Beauchene, H. Lapuyade, A. Touboul, F. Beaudoin, P. Perdu, Backside and front side picosecond OBIT mapping on ICs, Application for single event transient studies, ESREF'2001, pp. 1471-1476
  [7] :  [PAP367]  S. Bychikhin, M. Litzenberger, R. Pichler, D. Pogany, E. Gornik , Thermal and free carrier laser interferometric mapping and failure analysis of anti-serial smart power ESD protection structures, ESREF'2001, pp. 1501-1506
  [8] :  [PAP368]  R. Petersen, W. De Ceuninck, L. De Schepper, O. Vendier, H. Blanck, D. Pons, A refined method to measure the thermal resistance of heterojunction bipolar transistors under high-power conditions , ESREF'2001, pp. 1591-1596
  [9] :  [PAP369]  J.M. Bosc, Integrated power transistor size optimisation, ESREF'2001, pp. 1671-1676.
 [10] :  [PAP370]  S. FORSTER, T. LEQUEU, R. JERISIAN, Operation of power semiconductors under transient thermal conditions: thermal fatigue reliability and mechanical aspects, ESREF'2001, pp. 1677-1682.
 [11] :  [PAP371]  R. Schlegel, E. Herr, F. Richter, Reliability of non-hermetic pressure contact IGBT modules, ESREF'2001, pp. 1689-1694
 [12] :  [PAP372]  G. COQUERY, S. CARUBELLI, J.P. OUSTEN, R. LALLEMAND, F. LECOQ, D. LHOTELLIER, V. DE VIRY, PH. DUPUY, Power module lifetime estimation from chip temperature direct measurement in an automotive traction inverter, ESREF'2001, pp. 1695-1700
 [13] :  [PAP373]  G. GUFFROY, G. SIMON, A pragmatic methodology for the monitoring of the electronic components ageing :The case of power thyristors at EDF, ESREF'2001, pp. 1701-1705
 [14] :  [PAP374]  S. AZZOPARDI, A. KAWAMURA, H. IWAMOTO, O. BRIAT, J.M. VINASSA, E. WOIRGARD, C. ZARDINI, Local lifetime control IGBT structures : Turn-off performances comparison for hard- and soft-switching between 1200V trench PT- and new planar PT-IGBTs, ESREF'2001,
 [15] :  [PAP430]  Y. Rey-Tauriac, M. Taurin, O. Bonnaud, High reliability power VDMOS Transistors in Bipolar/CMOS/DMOS technology, ESREF'2001.
 [16] :  [PAP431]  Y. Rey-Tauriac, M. Taurin, O. Bonnaud, Wafer Level Accelerated test for ionic contamination control on VDMOS transistors in Bipolar/CMOS/DMOS, ESREF'2001.
 [17] :  [ART181]  U. SCHEUERMANN, E. HERR, A Novel Power Module Design and Technology for Improved Power Cycling Capability, ESREF'2001.


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