"SIERRA: a 3-D device simulator for reliability modeling", 1989.
Copyright - [Précédente] [Première page] [Suivante] - Home

Article : [SHEET131]

Titre : SIERRA: a 3-D device simulator for reliability modeling, 1989.

Cité dans :[THESE071] E. LORFEVRE, Défaillances induites par les rayonnements ionisants dans les composants de puissance IGBT et VIP. Solutions de durcissement, thèse de Doctorat, Montpellier, 30 octobre 1998.
Auteur : Chern, J.-H.;
Auteur : Maeda, J.T.;
Auteur : Arledge, L.A., Jr.;
Auteur : Yang, P. - Texas Instrum. Inc., Dallas, TX, USA

Appears : Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Pages : 516 - 527
Date : May 1989
Volume : 8
Issue : 5
ISSN : 0278-0070
CODEN : ITCSDI
Stockage : Thierry LEQUEU
Lien : private/CHERN.pdf - 1020 Ko.

Abstract :
SIERRA is a 3-D general-purpose semiconductor-device simulation
program which serves as a foundation for investigating
integrated-circuit (IC) device and reliability issues. This
program solves the Poisson and continuity equations in silicon
under DC, transient, and small-signal conditions. Executing on a
vector/parallel minisupercomputer, SIERRA utilizes a matrix
solver which uses an incomplete LU (ILU) preconditioned conjugate
gradient square (CGS, BCG) method. The ILU-CGS method provides a
good compromise between memory size and convergence rate. The
authors have observed a 5* to 7* speedup over standard direct
methods in simulations of transient problems containing highly
coupled Poisson and continuity equations such as those found in
reliability-oriented simulations. The application of SIERRA to
parasitic CMOS latchup and DRAM (dynamic random-access memory)
single-event-upset studies is described.<>

Subjet_terms :
IC device modelling; Poisson equations; DC conditions; transient
conditions; DRAM SEV studies; SIERRA; 3-D device simulator;
reliability modeling; general-purpose semiconductor-device
simulation program; reliability issues; continuity equations;
small-signal conditions; vector/parallel minisupercomputer;
matrix solver; incomplete LU; preconditioned conjugate gradient
square; ILU-CGS method; memory size; convergence rate; speedup;
transient problems; coupled Poisson and continuity equations;
reliability-oriented simulations; parasitic CMOS latchup; CMOS
integrated circuits; digital simulation; electronic engineering
computing; random-access storage; reliability; semiconductor device models

Accession_Number : 3442037

References : 36


Mise à jour le lundi 25 février 2019 à 15 h 36 - E-mail : thierry.lequeu@gmail.com
Cette page a été produite par le programme TXT2HTM.EXE, version 10.7.3 du 27 décembre 2018.

Copyright 2019 : TOP

Les informations contenues dans cette page sont à usage strict de Thierry LEQUEU et ne doivent être utilisées ou copiées par un tiers.
Powered by www.google.fr, www.e-kart.fr, l'atelier d'Aurélie - Coiffure mixte et barbier, La Boutique Kit Elec Shop and www.lequeu.fr.