S. WEN, L. M. KEER, "A Fatigue Theory for Solders", IRPS'2001, pp. 120-127.
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Article : [PAP254]

Titre : S. WEN, L. M. KEER, A Fatigue Theory for Solders, IRPS'2001, pp. 120-127.

Cité dans : [DIV214]  IRPS'2001, 2001 IEEE International Reliability Physics Symposium, 30 avril - 3 mai 2001, Orlando, Floride.
Auteur : Shengmin Wen
Auteur : Leon M Keer - Department of Civil Engineering, Northwestern University - 2145 Sheridan Road, Evanston, IL 60201, USA

Stockage : Thierry LEQUEU Bibliothèque LMP.
Pages : 120 - 127
Date : 30 avril - 3 mai 2001
Lien : private/WenKeer.pdf - 4090 Ko, 8 pages.
Keywords : fatigue, solders, percolation, micromechanics, anisotropic, size effect.

ABSTRACT :
A fatigue theory with its definition of fatigue failure criterion based
on physical damage mechanisms is presented for solders. The theory
applies Mura’s micromechanical fatigue model to each individual
grain of the solder structure, where grain’s crystallographic
orientation is taken into account. A solder structure is defined as
fatigued when the ratio of its failed grains reaches a critical
percolation threshold, since at this point the failed grains may form a
large cluster. Experimental data for 96.5Pb-3.5Sn solder showed
good agreement with the prediction by the theory and its failure
criterion. The theory is anisotropic, and thus there is no size
limitation to its application, making it applicable to anisotropic
small-scale (micron scale or smaller) solder joints.

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Bibliographie

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  [1] :  [PAP158]  -------
  [2] : [THESE099] S. VAYNMAN, Isothermal fatigue of 96.5Pb-3.5Sn solder, Ph.D. Dissertation, Department of Materials Science and Engineering, Northwestern University, Evanston, IL, 1987.
  [3] :  [PAP158]  -------
  [4] :  [PAP158]  -------
  [5] : [THESE100] L. R. LAWSON, Thermomechanical fatigue of 97Pb-3Sn, Ph.D. Dissertation, Department of Materials Science and Engineering, Northwestern University, Evanston, IL, 1989.
  [6] :  [PAP256]  W.W. LEE, L.T. NGUYEN, G.S. SELVADURAY, Solder joint fatigue models: review and applicability to chip scale packages, Microelectronics Reliability, Vol. 40, No. 2, 2000, pp. 231-244.


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