E. HERR, H. BALTES, T. STOCKMEIER, U. THIEMANN, "Gate insulation yield loss due to lattice misfit stress in MCT and IGBT devices", ISPSD'93.
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Article : [ART249]

Info : REPONSE 10, le 13/05/2002.

Titre : E. HERR, H. BALTES, T. STOCKMEIER, U. THIEMANN, Gate insulation yield loss due to lattice misfit stress in MCT and IGBT devices, ISPSD'93.

Cité dans : [DATA240] Recherche sur l'auteur E. HERR, mai 2002.
Auteur : Herr, E. (ETH Zurich, Zurich, Switz)
Auteur : Baltes, H.
Auteur : Stockmeier, T.;
Auteur : Thiemann, U.

Meeting : Proceedings of the 5th International Symposium on Power Semiconductor Devices and ICs.
Info : organization : IEEE; Institute of Electrical Engineers of Japan
Location : Monterey, CA, USA
Date : 18 May 1993-20 May 1993
Source : Proceedings of the 5th International Symposium on Power Semiconductor Devices and IC's Proc Int Symp Power Semicond Devices ICs 1993.Publ by IEEE, IEEE Service Center, Piscataway, NJ, USA.
Pages : 95 - 100
ISBN : 0-7803-1314-3
Année : 1993
Meeting_Number : 19271
Document_Type : Conference Article
Treatment_Code : Experimental
Language : English
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Abstract :
A high-dose boron implantation prior to the gate oxidation is found
to be responsible for significantly reduced breakdown field strengths
observed for gate oxides in MCT (MOS Controlled Thyristor) and IGBT
devices.A failure mechanism based on lattice misfit stress and
implantation damage below the amorphization threshold is proposed, which
explains the observation that breakdown events exclusively occur at the
very periphery of the implanted regions.This is in accordance with the
scaling law that is found, exhibiting a logarithmic relationship between
the breakdown strength of MOS capacitors and the perimeter length of p
plus regions in the substrate.These defect-related failures do not occur,
if the p plus -implantations respective their annealings are conducted
appropriately.(Author abstract)

Références : 14 Refs.

Accession_Number : 1993(51):5890 COMPENDEX


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