Y.S. CHUNG, B. BAIRD, "Power capability limits of power MOSFET devices", Microelectronics Reliability, Volume 42 , Issues 2, February 2002, pp. 211-218.
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Titre : Y.S. CHUNG, B. BAIRD, Power capability limits of power MOSFET devices, Microelectronics Reliability, Volume 42 , Issues 2, February 2002, pp. 211-218.

Cité dans :[REVUE294] Elsevier Science, Microelectronics Reliability, Volume 42, Issue 2, Pages 157-305, February 2002.
Cité dans : [DIV334]  Recherche sur les mots clés power cycling of power device, mai 2002.
Auteur : Young S. Chung
Auteur : Bob Baird

Vers : Bibliographie
Adresse : SMARTMOS Technology Center, DigitalDNA Laboratory, Motorola 2200 W. Broadway Rd. M350, Mesa, AZ 85202, USA
Tel. : +1-480-655-4425
Fax. : +1-480-655-4342
Lien : mailto:young.chung@motorola.com
Source : Microelectronics Reliability
Volume : 42
Isues : 2
Date : February 2002
Pages : 211 - 218
DOI : 10.1016/S0026-2714(01)00252-9
PII : S0026-2714(01)00252-9
Lien : private/CHUNG1.pdf - 8 pages, 352 Ko.
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Abstract :
With technology progression, power capability becomes a more critical concern in
optimizing power device designs in various smart power IC applications.
Interaction between the electrical and thermal entities is essential in
understanding the power capability limit of the semiconductor devices in both
transient and steady-state operations. This paper reports the fundamental
mechanisms of the electrical¯thermal coupling process during power dissipation
and the characteristics of the power capability limits of the power MOSFET
devices from the scope of intrinsic and extrinsic factors that affect the power
capability. An electrothermally driven snapback breakdown is discussed in detail
to investigate the physical mechanism of the power capability limits of an LDMOS
power transistor. Both simulation and experimental results are in good
agreement, indicating that the electrothermal snapback breakdown would occur at
lower junction temperature than the intrinsic junction temperature.

Article Outline
1. Introduction
2. Device structure and simulation
3. Experimental
4. Discussion
5. Conclusion
Acknowledgements


Bibliographie

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Références : 11
[1] : V. Dwyer, A. Franklin and D. Campbell , Thermal failure in semiconductor devices. Solid State Electron 33 (1990), pp. 553¯560.
[2] : G. Watchutka , Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modeling. IEEE Trans CAD 11 (1990), pp. 1141¯1149.
[3] : Rodrigues RG, et al. Operation of power semiconductors at their thermal limit. 33th Industry Applications Conference, vol. 2. 1998. p. 942¯53.
[4] : M. Trivedi and K. Shenai , Failure mechanisms of IGBTs under short-circuit and clamped inductive switching stress. IEEE Trans Power Electron 14 1 (1999), pp. 108¯116. Abstract-INSPEC | Abstract-Compendex | Full-text via CrossRef
[5] : Z.J. Shen, D. Briggs and S.P. Robb , Voltage dependence of self-clamped inductive switching (SCIS) energy capability of IGBTs. IEEE Electron Dev Lett 21 3 (2000), pp. 119¯122. Abstract-Compendex | Abstract-INSPEC | Full-text via CrossRef
[6] : Merchant S et al. Energy capability of lateral and vertical DMOS transistors in an advanced automotive smart power technology. ISPSD '98. 1998. p. 317¯20.
[7] : Farenc D et al. Clamped inductive switching of LDMOST for smart power ICs. ISPSD '98. 1998. p. 359¯62.
[8] : Chung Y et al. Energy capability of power devices with Cu layer integration, ISPSD '99. 1999. p. 63¯6; Transient thermal simulation of power devices with Cu layer. ISPSD '99. 1999. p. 63 and 257¯60.
[9] : Hower P et al. Snapback and safe operating area of LDMOS transistors, IEDM'99. 1999. p. 193¯6; Avalanche-induced thermal instability in LDMOS transistors. ISPSD '01. 2001. p. 153¯6.
[10] : Y.S. Chung and B. Baird , Electrical¯thermal coupling mechanism on operating limit of LDMOS transistor. Tech Digest IEDM (2000), pp. 83¯86. Abstract-Compendex | Abstract-INSPEC
[11] : Chung YS, Valenzuela O, Baird B. Mechanism of power dissipation capability of power MOSFET devices: comparative study between LDMOS and VDMOS transistors. ISPSD 2001. p. 275¯8.


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