M. AMAGAI, "Chip Scale Package (CSP) solder joint reliability and modeling", Microelectronics and Reliability, Volume 39, Issue 4, April 1999, pp. 463-477.
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Article : [PAP464]

Titre : M. AMAGAI, Chip Scale Package (CSP) solder joint reliability and modeling, Microelectronics and Reliability, Volume 39, Issue 4, April 1999, pp. 463-477.

Cité dans :[REVUE236] Elsevier Science, Microelectronics Reliability, Volume 39, Issue 4, Pages 441-549, April 1999.
Cité dans :[PAP360]
Auteur : M. Amagai

Adresse : New Package Development (NPD) Department, Texas Instruments Japan, 4260 - Kawasaki, Hiji-machi, Hayami-gun, Oita 879-1595, Japan
Tel. : +81-977-73-1729
Fax. : +81-977-73-1582
Lien : mailto:amai@ti.com
Source : Microelectronics and Reliability
Volume : 39
Issue : 4
Date : April 1999
Pages : 463 - 477
Info : Received 7 August 1998; revised 3 February 1999. Available online 21 June 1999.
Lien : private/AMAGAI.pdf - 372 Ko, 15 pages.

Abstract :
A viscoplastic constitutive model was used to analyze the thermally induced
plastic and creep deformation and low cycle fatigue behavior of the solder
joints in Chip Scale Packages (CSP) mounted on Printed Circuit Boards (PCB). The
time-dependent and time-independent viscoplastic strain rate and plastic
hardening work factors of solder material were used in 2-D plane strain finite
element models. The viscoplastic strain rate data was fitted to the viscoplastic
flow equation. The plastic hardening factors were considered in the evolution
equation. A viscoelastic constitutive model was used for molding compound.
Finite element models, incorporating the viscoplastic flow and evolution
equations for solder and the viscoelastic equations for molding compound, were
verified by temperature cycling tests on assembled CSPs. The effect of the
cyclic frequency, dwell time, and temperature ramp rate on the response of the
viscoplastic deformation was studied for a tapeless Lead-on-Chip (LOC) CSP and a
flexible substrate CSP. The ramp rate significantly affects the equivalent
stress range in solder joints while a dwell time in excess of 10 min per half
cycle does not result in increased strain range. The failure data from the
experiments was fitted to the Weibull failure distribution and the Weibull
parameters were extracted. After satisfactory correlation between the experiment
and the model was observed, the effect of material properties and package design
variables on the fatigue life of solder joints in CSPs was investigated and the
primary factors affecting solder fatique life were subsequently presented.
Furthermore, a simplified model was proposed to predict the solder fatigue life in CSPs.

Keywords : Chip Scale Package; Solder fatique; Creep; Viscoplasticity; Viscoelasticity; Extrapolation; Finite element method

Article Outline


1. Introduction
2. Chip Scale Packages
3. Solder fatigue cracking
4. Modeling methodology
4.1. Molding compound and viscoelastic modeling
4.2. Solder material and viscoplastic modeling
4.2.1. Model
4.2.2. Material property
4.3. Other materials
5. Finite element analysis
6. Design and model simplification
7. Conclusion



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