1997 International




October 13-16, 1997
Stanford Sierra Camp, S. Lake Tahoe, CA U.S.A.


IEEE Electron Device Society & Rel Society


Workshop Experience

Major Technical Themes

Keynote Address

Discussion Groups


Open Poster Sessions

Special Interest Groups

Technical Program

JEDEC Committee 14.2 Meeting (Oct. 15-16)

Miscellaneous Information

Registration Form


Workshop Experience

You are cordially invited to participate in the 1997 Integrated Reliability Workshop. The Workshop provides a unique forum for sharing new approaches to achieve and maintain microelectronic component reliability. The Workshop features presentations, tutorials, open poster sessions, moderated discussion group sessions, and special interest group (SIG) meetings. All Workshop activities take place in a relaxed and rustic setting that promotes an atmosphere of interactive learning and knowledge sharing.

Major Technical Themes

As silicon technology continues aggressively to scale into the deep submicron regime, physical models for reliability need to be continually revised and expanded to include more complex device and materials behavior. Reflecting this need, the Contributors to Failure session includes several papers on thin oxide reliability modeling. The Reliability Test Structures session complements this focus with papers on area effect and antenna damage monitoring structures. Designing-in Reliability is a methodology that is being incorporated at earlier stages of the process development cycle. The balancing of technology requirements requires simultaneous assessment of device reliability and performance. This task is made easier with the help of modeling tools. The tools of Wafer Level Reliability continue to be crucial to the task of technology reliability development and monitoring. Techniques are constantly refined to meet the ever-changing behavior and test requirements.


Benchmarking Semiconductor Manufacturing

Professor David A. Hodges
University of California, Berkeley

Professor David Hodges is co-director of the Competitive Semiconductor Manufacturing Program at UC Berkeley. The CSM program brings together faculty and students from Berkeley's College of Engineering, Haas School of Business, and Department of Economics in a continuing program addressing key aspects of semiconductor manufacturing. The program has several elements:

Comparative studies of the world's best semiconductor plants to identify world-class managerial, organizational, technical, and human resource practices.

Specific research projects focused on improving key semiconductor manufacturing processes and related business and management practices.

A dissemination program that has produced 33 research reports, a similar number of conference presentations and archival publications, and three professional short courses targeted at managers and engineers in the semiconductor industry.

The goal of the main comparative study, begun in 1992, is to develop a systematic account of the practices which explain best manufacturing performance in semiconductor production on a world-wide basis. The effort has established comparative benchmarks and performed comparative evaluation along dimensions of technology, business practices, and business environment.

Discussion Groups

A highlight of the Workshop is the evening discussion group program. Attendees will have a choice of four topics on both Tuesday and Wednesday evenings. The same four topics will be discussed for 90 minutes each night. This year's topics are:

Designing in Reliability
Leaders: Mark Poulter, National Semiconductor and Riko Radojcic, Cadence, Angora Room

The motto is: Process Qualification without Product Qualification. The traditional method of qualifying a new process comes late in the development cycle. It is achieved by running qualification on a few lots of a product which exercises the main features of the process. If there are failures, much time and money is wasted in implementing process improvements and performing requalification. In the constant push to reduce development cycle times, methods must be implemented to start qualification of the process well in advance of any product. Identifying and fixing reliability problems early avoids the need for costly requalification and the unacceptable delays it incurs.

In this discussion group we will consider how to perform process qualification without product qualification by asking:

Wafer Level Reliability
Leader: Cleston Messick, National Semiconductor and
Sally Yankee, IBM,
Cathedral Room

The idea of Wafer Level Reliability (WLR) first appeared in the early 80's. After much discussion and many programs, the definition of WLR still eludes consensus. During this discussion session, several definitions will be presented and discussed. Attendees are invited to bring their own definitions and examples of successful implementations and/or examples of failures in implementation. The participants will gain a greater appreciation for the abilities and limitations of WLR along with a concrete understanding of the definition of WLR.

Customer Reliability Requirements
Leaders: Andreas Preussger, Siemens and Ian Wylie, Northern Telecom, Tallac Room

Suggested topics for discussion:

Reliability Test Structures
Leaders: Tim Turner, Keithley Instruments and Jim Lloyd, Lloyd Technologies, Old Lodge

Test structures for reliability evaluations are taking an increasingly important position in reliability assurance programs for semiconductor products. The design of these test structures is not a trivial task. While the structures are generally fairly basic circuit elements, the restrictions imposed by anomalous failure mechanisms and stress limitations require a very detailed knowledge of the failure mechanism to be studied and the process used to build these structures. A few potential discussion topics associated with the use of these test structures are listed below.


In our continuing effort to enhance the value of the Workshop and to strengthen the Technical Program, we are again offering two tutorials on Monday afternoon.

Tutorial A:

Determination of physical parameters and reliability of ultra thin gate oxides E. Cartier, IBM Research Division, T.J. Watson Research Center, Yorktown Heights, NY

The aggressive down scaling of the device dimensions in CMOS technology will require the fabrication of gate oxides with thickness in the range of 2-3 nm in the near future and the fabrication of oxides with an equivalent thickness of less than 2 nm will eventually be required. To characterize such thin oxides, well established techniques may no longer provide accurate results or can not be used at all. In this tutorial, some issues related to the characterization of very thin oxides will be addressed.

Tutorial B:

Device design methodology and reliability strategy for deep submicron technology Rama Divakaruni, Badih El-Kareh*, and William Tonti, IBM Microelectronics and *IBM Strategic Technologies

This tutorial will discuss device and process optimization techniques that may be employed in the design of present state of the art bulk Si DRAM technology. MOSFET performance and reliability issues are contrasted.

The topical issues to be discussed include:

Open Poster Sessions

The Technical Program will include two open poster sessions. All attendees have the opportunity to present a poster to communicate their ideas and results on a technical project or issue. Please indicate your intention to bring a poster by reserving a poster display board (32" x 40" or 81 cm x 100 cm) in the space provided on the registration form. Your work should be in Landscape format on 8½ x 11" or A4 paper with a maximum of twelve pages. In addition, you are invited to submit a two-page abstract of your poster presentation for inclusion in the Workshop Final Report. This is a great opportunity for you to share your work with your peers.

Special Interest Groups (SIG)

The SIG program at the Workshop has been very successful in fostering collaborative work on important reliability issues and we look forward to continuing growth and renewal in our SIGs. The formation of SIGs is encouraged as a natural extension of the Discussion Group sessions. Anyone interested in more information about SIGs is encouraged to contact the 1997 SIG Coordinator, Jiang Tao at jtao@grape.amd.com.

JEDEC 14.2 Meeting

The JEDEC 14.2, Wafer Level Reliability Standards Committee, meeting will be held immediately after the Workshop at the Stanford Sierra Camp on Thursday afternoon and Friday morning. Members, alternates, and guests are welcome. The cost for the accommodations is $160.00, which includes Thursday night dinner and lodging and Friday breakfast and lunch. All attendees must leave the camp after lunch on Friday. If you have any questions or if you want to become a member of JC-14.2, please call the JEDEC office at (703) 907-7558 or call Mike Dion, JC-14.2 Chair, at (704) 724-7067.

More Information

We expect an exciting workshop again this year. We look forward to your active participation in the many Workshop activities and your valuable contribution to the technical program. If you have any questions, please contact the Technical Program Chair, Raif S. Hijab, by phone, 408-749-2250, or fax, ...5585, or e-mail: raif.hijab@amd.com, or the General Chair, James W. Miller, at 512-933-7297, fax...7662, email: rvkg60@email.sps.mot.com


Complete and mail the enclosed registration form. Please register early. We were nearly sold out last year. Space at the Camp limits the Workshop to roughly 120 attendees.

We look forward to seeing you at the '97 Workshop!

Raif S. Hijab
Technical Program Chair