1:00-8:00 p.m. Lodge check-in. Get room assignment (preassigned) & room key, with lodge area map and information.
(ADA please notify desk of special needs)
1:00-2:30 p.m. Registration: Pick up badges & handout
(Dining Room Lounge)
Sign up for Discussion Groups and SIG meeting
2:30-4:30 p.m. Tutorial Sessions
Tutorial A: Determination of Physical Parameters and Reliability of Ultra Thin Oxides
E. Cartier, IBM, Yorktown Heights, NY Angora Room
Tutorial B: Device Design Methodology and Reliability Strategy
for Deep Submicron Technology
Rama Divakaruni, Badih El Kareh*, and William R. Tonti,
IBM Microelectronics and *IBM Strategic Technologies, Cathedral Room
4:30-6:00 p.m.Registration: Pick up badges & handout (Dining Room Lounge)
Sign up for Discussion Groups and SIG meeting
5:00-6:00 p.m. Mixer & Poster Session, Cathedral Room
6:00-7:30 p.m. DINNER, Dining Room
7:00-7:30 p.m. Registration for late arrivals (Dining Room Lounge)
7:30-8:30 p.m. Mixer & Poster Session, Cathedral Room
8:30-9:30 p.m. SIG Meeting (all SIGs), Angora Room
TUESDAY, October 14
7:00 a.m. BREAKFAST (until 8:00 a.m.)
8:15-8:30 a.m. Welcome & Introduction: James W. Miller, General Chair,
and Raif S. Hijab, Technical Program Chair, Angora Room
8:30-9:45 a.m. Keynote: Benchmarking Semiconductor Manufacturing
Professor David Hodges,
EECS Dept, University of California, Berkeley
9:45-10:15 a.m. Break
10:15-11:30 a.m. Session #1: Contributors to Failure (CTF),
Paula O'Sullivan, NMRC, Chair, Harry Schafft, NIST, Vice Chair
CTF-1 Resistance Transients in Thin-film Noise Data
Linda M. Head,
SUNY at Binghamton
CTF-2 Plasma-Induced Polarity Dependent Hot-Carrier Response of
CMOS Devices Across a Wafer
B. Bhuva, V. Janapaty and S. Kerns, Vanderbilt University and
Nguyen Bui, Advanced Micro Devices
CTF-3 Acceleration Factors of PMOS Hot-Carrier Degradation
Hisao Katto,
Science University of Tokyo
11:30 a.m.-noon. Group Picture
noon-1:30 p.m. LUNCH, Dining Room
2:00-3:15 p.m. Session #2: Reliability Test Structures (RTS), Brian Langley, Hewlett-Packard, Chair
RTS-1 Investigation of the Intrinsic SiO2 Area Dependence using TDDB Testing
J. Prendergast, Nuala Finucane, Analog Devices, and
John Suehle, NIST
RTS-2 Antenna Damage from a Plasma TEOS Deposition Reactor:
Relationship with Surface Charge and RF Sensor Measurements
Indira J. Gupta, Kelly Taylor, Dave Buck and Srikanth Krishnan,
Texas Instruments
RTS-3 Optimized Application of Antenna Structures in a WLR Monitoring Program
W. Asam, J. Fazekas and J. von Hagen,
Siemens AG
3:15-3:45 p.m. Break
3:45-5:00 p.m. Session #3: Designing In Reliability (DIR),
Bill Vigrass, Texas Instruments, Chair, Homi Nariman, AMD, Vice Chair
DIR-1 CMOS Transistor Reliability and Performance
Impacted by Gate Microstructure
Bin Yu, Dong-Huyk Ju*, Nick Kepler*, Tsu-Jae King, and Chenming Hu,
University of California, Berkeley *Advanced Micro Devices
DIR-2 Designing-in Device Reliability during the Development of
High-Performance CMOS Logic Technology from 0.5 µm to 0.13 µm
Deepak K. Nayak, Ming-Yin Hao, and Raif Hijab,
Advanced Micro Devices
DIR-3 HCI Lifetime Enhancement by Double Implanted S/D of Nch MOSFET
in 0.25 µm CMOS Technology
David Wu, Scott Luning, D. H. Ju, and Nick Kepler,
Advanced Micro Devices
5:00-6:00 p.m. Mixer & Poster Session
6:00-7:30 p.m. DINNER, Dining Room
7:30-9:00 p.m. Discussion Groups (90 minute parallel sessions for each topic)
Attendees are to participate in one of the four groups
9:00-10:30 p.m. Individual SIG Meetings
WEDNESDAY, October 15
7:00 a.m. BREAKFAST (until 8:00 a.m.)
8:15-8:30 a.m. Announcements, Angora Room
8:30-10:10 a.m. Session #4: Contributors to Failure (CTF)
CTF-4 Effect of Electronic Corrections on the Thickness Dependence of
Thin Oxide Reliability
G. B. Alers, A.S. Oates, B. E. Weir, D. Monroe, and K. S. Krisch,
Bell Labs, Lucent Technologies
CTF-5 The Non-uniqueness of Breakdown Distributions in Silicon Oxides
J. C. Jackson, T. Robinson, O. Oralkan, D.J. Dumin, Clemson University and
G. A. Brown, Texas Instruments
CTF-6 Temperature Dependence of Gate Current in Ultra Thin SiO2 in
Direct-Tunneling Regime
A. Yassine and Raif Hijab,
Advanced Micro Devices
CTF-7 Charge-to-Breakdown and Trap Generation Process in Thin Oxides
Gennadi Bersuker, James Werking, and Sang Kim,
SEMATECH
(corrected pages for Final Report)
10:10-10:30 a.m. Break
10:30 a.m.-
12:10 p.m. Session #5: Wafer Level Reliability (WLR),
Prasad Chaparala, National Semiconductor, Chair, Sharad Prasad, LSI Logic, Vice Chair
WLR-1 A New Technique to Extract TDDB Acceleration Parameters from
Fast Qbd Tests
Y. Chen, John S. Suehle*, Bruce Shen, Joseph Bernstein, and
Cleston Messick**,
University of Maryland *NIST ** National Semiconductor
WLR-2 Correlation of Charge to Breakdown Obtained from
Constant Current Stresses and Ramped Current Stresses, and the
Implications for Ultra-Thin Gate Oxides
Nels Dumin,
Texas Instruments
WLR-3 A Candid Comparison of the SWEAT Technique and the
Conventional Test Procedure
for Electromigration Study in Sub-Half Micron ULSI Interconnects
Satish S. Menon and Ratan K. Choudhury,
LSI Logic
WLR-4 High Resolution Electromigration Measurements for
Reduction of the Test Time
Catherine de Keukeleire and Piet De Pauw, ALCATEL MIETEC and
Luc Tielemans, DESTIN N.V.
12:15-1:30 p.m. LUNCH, Dining Room (Take out LUNCH bags available)
The afternoon is free for discussion, hiking and other recreation
1:30-6:00 p.m. Open
6:00-7:30 p.m. DINNER, Dining Room
7:30-9:00 p.m. Discussion Groups (90 minute parallel sessions for each topic)
Attendees are to participate in one of the four groups
9:00-10:30 p.m. Individual SIG Meetings
THURSDAY, October 16
7:00 a.m. BREAKFAST (until 8:00 a.m.)
8:15-8:30 a.m. Announcements, Angora Room
8:30-10:10 a.m. Session #6: Wafer Level Reliability
WLR-5 A Novel In-process Wafer-Level Screening Technique for CMOS Devices
I. Yoshii, H Hazama, H. Kamijo, Y. Ozawa, and K. Hama,
Toshiba Corp.
WLR-6 Pulsed BTS - an Accurate and Fast Technique to Determine
Mobile Ion Concentrations and Kinetics in Gate and Field Oxides
Laszlo Gutai,
Philips Electronics North American
WLR-7 Charge Pumping for DRAM Retention Diagnostics
Rama Divakaruni and Jim Adkisson,
IBM Microelectronics
9:45-10:00 a.m. Break (checkout at this time if not staying for JEDEC meeting)
10:00-10:50 a.m. Session #7: Design-In Reliability
DIR-4 Automated Extraction of Parasitic BJTs for CMOS I/O Circuits
Under ESD Stress
Tong Li, Y. J. Huh, and S. M. Kang,
University of Illinois at Urbana-Champaign
DIR-5 Evolution of BSIM3v3 Parameters During Hot-Carrier Stress
Sean Minehane, Paula O'Sullivan, Alan Mathewson, and Barry Mason*,
National Microelectronics Research Centre (NMRC), and
*GEC Plessey Semiconductors
10:50-11:05 a.m. SIG Report
11:05-11:35 a.m. Discussion Group Summaries
11:35 a.m. - noon Wrap-Up
noon-1:30 p.m. LUNCH, Dining Room
Workshop Ends
Leave the Stanford Sierra Camp unless attending JC14.2
2:00 p.m. JEDEC 14.2 Committee on Wafer Level Reliability Meeting