L. ANGHEL, "Les limites technologiques du silicium et tolérance aux fautes", le 15 décembre 2000, INPG, Grenoble.
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Titre : L. ANGHEL, Les limites technologiques du silicium et tolérance aux fautes, le 15 décembre 2000, INPG, Grenoble.

Auteur : Lorena ANGHEL
Date : le 15 décembre 2000

Origine : INSTITUT NATIONAL POLYTECHNIQUE DE GRENOBLE, pour obtenir le grade de DOCTEUR DE L'INPG
Spécialité : « MICROELECTRONIQUE»
Préparée : au laboratoire TIMA dans le cadre de l'Ecole Doctorale « Electronique, Electrotechnique, Automatique, Télécommunications, Signal »

Directeur : Mihail Nicolaidis
Président : M. Guy Mazare
Rapporteur : M. Yervant Zorian
Rapporteur : M. Matteo Sonza-Reorda
Jury : Mihail Nicolaidis - Directeur de thèse
Jury : M. Eric Dupont - Examinateur

Lien : LTS_114.pdf - 742 Ko, 162 pages.
Spécialité : MICROELECTRONIQUE
Mots-clés : TOLERANCE AUX FAUTES, FAUTES TRANSITOIRES, FAUTES DE TIMING, CIRCUITS AUTO-CONTROLABLES, TECHNOLOGIES SOUSMICRONIQUES, REDONDANCES TEMPORELLES
ISBN : 2_913329_54_3 broché
ISBN : 2_913329_55_1 format électronique

RESUME :
Les technologies de silicium s’approchent de leurs limites physiques en termes de réduction de tailles des
transistors, et de la tension d’alimentation (VDD), d’augmentation de la vitesse de fonctionnement et du
nombre de dispositifs intégrés dans une puce. En s’approchant de ces limites, les circuits deviennent de plus
en plus sensibles à toute source de bruit (telles que les couplages capacitifs ou «cross-talks », l’influence
électro-magnétique, le bruit sur les lignes d’alimentation « ground-bounce »), ainsi qu’aux phénomènes
radiatifs (particules alpha et neutrons atmosphériques).
Ainsi, le taux d’erreurs du fonctionnement causées par l’impact des particules ionisantes (erreurs soft) ou par
des défauts difficiles à détecter échappant ainsi au test de fabrication (par ex. fautes temporelles), se voit
augmenté de façon radicale. Dans cette thèse, nous analysons dans un premier temps ces problèmes et nous
concluons que tout circuit doit être conçu en utilisant des techniques de tolérance aux fautes afin de pouvoir
maintenir des niveaux de fiabilité acceptables pour les prochaines générations de circuits nanométriques.
Cette analyse montre que les parties logiques tendent de devenir aussi sensibles aux erreurs soft que les
mémoires, nécessitant ainsi le même niveau de protection. Les techniques traditionnelles de tolérance aux
fautes (TMR, duplication) étant trop coûteuses, ne sont pas acceptables pour les applications à faible valeur
ajoutée (ex. produits grand publique). Le caractère temporel des fautes transitoires et de timing est exploité
afin de proposer des solutions efficaces utilisant des structures self-checking, ainsi que des techniques de
redondance temporelle. Ces techniques minimisent le coût matériel et ont un faible impact sur la vitesse de
fonctionnement du circuit. Nous avons aussi développé une méthodologie de simulation de fautes transitoires,
qui nous a permit d’évaluer de façon précise l’efficacité de protection obtenue par ces techniques.

TITRE_en_anglais : FAULT TOLERANCE VERSUS TECHNOLOGICAL LIMITATIONS OF SILICON
RESUME_EN_ANGLAIS :
Integrated circuit technology is approaching the ultimate limits of silicon in terms of geometry shrinking,
power supply level, speed and density. By approaching these limits, circuits are becoming increasingly
sensitive to any noise source (such as cross-talks, electromagnetic influence, noise on the power line, ground
bounce) as well as radiative phenomena (e.g. alpha particles and atmospheric neutrons).
Thus, the error rate due of the impact of ionizing particles (soft errors) or by the defects difficult to detect that
may escape fabrication testing (e.g. timing faults) is drastically increased. In this thesis, we address these
problems and we conclude that future integrated circuits have to be designed by using fault tolerance
techniques, in order to maintain acceptable reliability levels. This analyze shows that logic parts are becoming
as sensitive to soft errors as memories and therefore they need tobe protected. Traditional fault tolerance
techniques (e.g. TMR, duplication) are of a high cost, they are not acceptable for low added value applications
(for example commercial products). The temporal nature of the transient and timing faults is exploited in
order to obtain efficient solutions by using self-checking structures as well as time redundancy techniques.
These techniques decrease the hardware cost and have a small impact on the circuit performances. We have
also developed a transient fault simulation methodology, which has allowed us to evaluate the efficiency of
these methods with a very good accuracy.

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