F. UDREA, A. POPESCU, W. MILNE, "3D RESURF junction", 1998.
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Article : [SHEET138]

Info : COMPENDEX Numéro de réponse 18 - 22/02/2000

Titre : F. UDREA, A. POPESCU, W. MILNE, 3D RESURF junction, 1998.

Cité dans : [DATA036] Recherche sur les mots clés 3D simulation with ISE for semiconductor, 2000.
Cité dans : [CONF052] CAS, International Semiconductor Conference, mars 2002.
Auteur : Udrea, F. (Cambridge Univ, Cambridge, UK)
Auteur : Popescu, A.
Auteur : Milne, W.

Title : Proceedings of the 1998 International Semiconductor Conference, CAS.Part 1 (of 2).
Location : Sinaia, Romania
Date : 06 Oct 1998-10 Oct 1998,
Organization : IMT 1998.IEEE, Piscataway, NJ, USA.
Pages : 141 - 144
CODEN : 002310
Meeting_Number : 49875
Document_Type : Conference Article
Treatment_Code : Theoretical
Language : English
Stockage : Thierry LEQUEU
Lien : private/UDREA.pdf - 4 pages, 357 Ko.

Abstract :
This paper reports a new device concept - the 3D RESURF junction,
which is applicable to a large class of power devices which we term
3D power devices.The new class of devices features considerably
superior breakdown performance compared to any lateral power devices
reported to date and challenges the state-of-the art vertical
devices such as the VDMOSFET.The 3D Double Gate devices also benefit
by having a low on-resistance due to carrier modulation in the drift
region.The 3D RESURF is demonstrated numerically through extensive,
advanced 2-D and 3-D simulations. (Author abstract).

Accession_Number : 1999(16):5545

ISBN : 0-7803-4432-4
IEEE Catalog Number: 98TH8351
References : 9
Accession_Number : 6269758

Abstract :
This paper reports a new device concept-the 3D RESURF junction,
which is applicable to a large class of power devices which we
term 3D power devices. The new class of devices features
considerably superior breakdown performance compared to any
lateral power devices reported to date and challenges the
state-of-the art vertical devices such as the VDMOSFET. The 3D
Double Gate devices also benefit by having a low on-resistance
due to carrier modulation in the drift region. The 3D RESURF is
demonstrated numerically through extensive, advanced 2-D and 3-D
simulations.

Subjet_terms :
power semiconductor devices; 3D RESURF junction; 3D power device;
3D double gate device; on-resistance; carrier modulation; 2D
numerical simulation; 3D numerical simulation; breakdown voltage;
lateral power device


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