Monday, June 4, 17:00-18:15, 5F Main Hall

Chairperson: G. Charitat, LAAS-CNRS

                    R. Saito, Hitachi

4.1   Lead-Frame-On-Chip Offers Integrated Power Bus and Bond over Active Circuit

        T.R. Efland, D. Abbott, V. Arellano*, M. Buschbom, M. Chang**, C. Hoffart, L. Hutter, Q. Mai, I. Nishimura***, S.Pendharker, M. Pierce, C.C. Shen, C.M. Thee**** and H.Vanhorn

        Texas Instruments, U.S.A., *Texas Instruments, Mexico, **Texas Instruments, Taiwan, ***Texas Instruments, Japan and ****Texas Instruments, Malaysia

4.2   A Dimple-Array Interconnect Technique for Power Semiconductor Devices

        S.S. Wen and G.-Q. Lu

4.3   Novel Monitoring Method and Long-Term Reliability Evaluation of Power Semiconductor Devices in Power Utilities

        T. Horiuchi and Y. Sugawara