Increased performance and reduced cost these have driven rapid growth and unprecedented technical innovation in the semiconductor industry. To meet these demands, new materials and processes must be introduced for deep-submicron integrated circuit technology. These new materials necessitate new and revised physical models for reliability. Reflecting this need, discussion groups will focus on Cu metal and low-k dielectrics, ultra-thin oxides, ESD and new C-V techniques for reliability. The technical program includes a designing-in reliability session with papers on thermal modeling, Cu reliability, via reliability and stress voiding. A contributors to failure session provides papers on physical models for ultra-thin dielectric reliability. A reliability test structures session has papers on ESD and several novel techniques to assess plasma damage. A WLR session provides papers on oxide breakdown in a 64MB DRAM, and a new CV characterization technique. There are also tutorials on analysis of oxide data and DRAM design for reliablility.