Moderators: Udo Schwalke (Siemens) and Barton Gordon (Materials Development Corporation)

For several decades, the capacitance-voltage (C-V) method has been a popular tool to study semiconductor and oxide properties. For example, the extraction of SiO2/Si interface state densities together with their distribution in the band gap and the determination of fixed oxide charges provided useful information for the understanding of MOS degradation phenomena and oxide breakdown. However, after so many years, is the C-V method still of interest and what is currently its implication on oxide, transistor and non-volatile memory cell reliability? It is the aim of the discussion group to sample the present extent of use of C-V techniques among the participants, discuss possible applications of C-V measurements within the framework of MOS reliability and evaluate some recent developments in the field of C-V measurements.

Discussion Topics:

• Ultra thin gate oxides: How to measure the oxide thickness accurately?
• Impact of slow traps on quasi-static C-V characteristics: What do I measure?
• Drawbacks of a fixed ramp rate: Waste of time and loss of information?
• Minority carrier lifetime, deep-depletion profiling: Monitoring Si damage?
• Limits of C-V measurements and their correlation to reliability testing.
• Problems inherent in measurements of very thin or very thick oxides.
• Is C-V dead?
• Will C-V be replaced by non-contact techniques?