Moderators: Horst Gieser (Fraunhofer IFT) and Steve Voldman (IBM)
Electrostatic Discharge is one of the major yield and reliability concerns for present and future technologies. The DC-breakdown voltages of gate oxides go below the trigger voltages of pn-junctions used for protection. Thus, the realization of effective protection elements becomes a real challenge and the risk of ESD damage in the core increases, especially for Charged Device Model (CDM) events. Increased amounts of energy and discharge current should be handled safely by smaller protection structures with minimum parasitic effects on the RF-performance. High pin counts, chip size packages and CDM-situations are raising many questions on how to protect these devices and how to test and qualify their ESD-protection reliability. Demanding development cycle times do not allow the trial-and-error method while calling for better wafer level (test) methods and more effective use of electro-thermal simulations. The discussion group intends to discuss the current approaches for these problems and to identify future needs with possible solutions.
Further topics of interest may be: