Dear IRW´98 attendee,
This year the following four discussion groups are organised for the workshop:
You can attend two of the 90min. discussion groups during the workshop.
Please make your choice of two groups and state them on the registration
form. Also you should be prepared participating in the discussion. Bring
along material regarding the discussion group topics which is of interest
for you because of open questions or unusual observations. In addition the
discussion group moderators have compiled a short questionnaire for each group
in order to include your interests in the discussion and to assess your
level of expertise. Your participation is highly desired. I am looking
forward seeing you at IRW´98.
(IRW´98 Discussion Group Chair)
Discussion group moderators: Tim
Sullivan, IBM, U.S.A. and Carl Thompson, MIT, U.S.A.
To meet anticipated requirements over the next 15 years, the U.S. National Technology Roadmap for Semiconductors charts an aggressive path for evolution of current interconnect technology. Insertion of new interconnect materials (Cu as the primary conductor, with refractory metal liners) is already underway, and, to stay on the NTRS timeline, insertion of new dielectric materials will be required in the near future. With interconnect lengths of kilometers per circuit, minimum linewidths shrinking below 100nm, the number of metallization levels moving toward 10, and the use of an interconnect metal which must be fully isolated from the dielectric, enormous reliability challenges must be met during a period of rapid development of new materials and processes. The goals of this discussion group will be to identify areas of greatest concern, and share lessons learned, and anticipated needs.
Specific discussion topics will include:
Discussion group moderators: Rolf-Peter
Vollertsen, Siemens Comp. Inc., U.S.A. and Dave Dumin, Clemson University,
A lot of open questions still exist in the area of oxide reliability.
New aspects come into play when the oxide thickness is scaled down to only a
What should we mainly be measuring, electric or thermal (catastrophic dielectric) breakdowns; non-destructive, soft- or quasi breakdowns; intrinsic and/or extrinsic breakdowns; Qbd, Tbd or Ebd?
In really thin oxides, who cares if there are failures since intrinsic oxides conduct so much current anyway because it may be hard to tell when there is a short circuit in parallel with a leaky intrinsic oxide? Besides, a lot of bad things, like SILC's, Vt shifts, gm shifts, etc. happen long before intrinsic oxide failures. At the other hand aren't the extrinsic breakdowns much more important than the intrinsic?
What effects has the change of conduction mechanisms from Fowler-Nordheim to Direct Tunneling on oxide reliability? Especially, what effect has it on the reliability measurement methods? How for example, will SILC or any other leakage current at low fields be monitored during highly accelerated stress measurements?
How can a manufacturer sell a thin oxide with a low Qbd measured with the STANDARD reliability test when the customer still requires the old target specs? What are the realistic future targets of ultra thin oxide reliability? How can we measure them?
Other discussion topics of interest are:
Discussion group moderators: Horst
Gieser, Fraunhofer IFT, Germany and Eugene Worley, Rockwell International,
Electrostatic Discharge is one of the major yield and reliability
for present and future technologies. The DC-breakdown voltages of gate
oxides go below the trigger voltages of pn-junctions used for protection.
Thus, the realization of effective protection elements becomes a real
challenge and the risc for ESD damages in the core increases, especially
for Charged Device Model CDM events. Increased amounts of energy and
discharge current should be handeled safely by smaller protection
structures with minimum parasitic effects ON the RF-performance.
High pin counts, chip size packages and CDM-situations are raising many questions on how to protect these devices and how to test and qualify their ESD-protection reliably. Demanding development cycle times do not allow the trial-and-error method while calling for better wafer level (test) methods and effective use of electro-thermal simulations.
The discussion group intends to discuss the current approaches for these problems and to identify future needs with possible solutions.
Further topics of interest may be:
Discussion group moderators: Udo
Schwalke, Siemens AG, Germany and Barton Gordon, Materials Development
For several decades, the capacitance-voltage (C-V) method has been a
tool to study semiconductor and oxide properties. For example, the
extraction of SiO2/Si interface state densities together with their
distribution in the band gap and the determination of fixed oxide charges
provided useful information for the understanding of MOS degradation
phenomena and oxide breakdown. However, after so many years, is the C-V
method still of interest and what is currently its implication on oxide,
transistor and non-volatile memory cell reliability?
It is the aim of the discussion group to sample the present extent of use of C-V techniques among the participants, discuss possible applications of C-V measurements within the framework of MOS reliability and evaluate some recent developments in the field of C-V measurements.
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