1998 International

October 12-15, 1998
Stanford Sierra Camp, Lake Tahoe, CA 


The Integrated Reliability Workshop will focus on ensuring semiconductor reliability through component design, characterization and analysis tools. It provides a unique environment for envisioning, developing, and sharing reliability technology for present and future semiconductor applications.

One embodiment of these reliability tools is Wafer Level Reliability (WLR). WLR is most effective when a proven physical acceleration model is used in the design and application of reliability test structures, test methods, and stress conditions. This years' IRW will focus on the effective use of WLR to build-in reliability. To this end we wish to address what are the limits to WLR.

We invite you to submit a presentation proposal that addresses one or more of the following topics:

Identification of reliability effects: 
     failure mechanisms and sensitivities to materials and manufacturing.

Reliability models 
(existing/new) used to show: 
     experimental agreement between short-duration and long-duration test results, 
     limits to accelerated stress,  
     applications for AC, pulsed, and DC conditions.

Reliability test structures: 
     design, characterization, uses and data analysis; 
     integrated on-chip reliability test systems  (including electrical and/or physical test/analysis). 

Wafer level reliability tests and test approaches: 
     test and analysis methodologies, reduction in development time, 
     relation to circuit element and package tests, in-line monitors; 
     use and interpretation of WLR data; success stories; 
    learning achieved with WLR, the fine tuning of a WLR implementation.

Designing-in reliability 
  (circuits, processes, products): 
     methodologies and concepts, modeling, simulation tools, 
     reliability-driven design rules and checkers; 
     use of WLR for design rule verification.

Customer product reliability requirements:
     reliability evaluation methodologies; data bases; 
     reporting systems; future reliability targets. 

SUBMISSION DEADLINE: Received no later than July 3, 1998.

Please submit 15 copies of your two-page (maximum) presentation proposal (including figures). Your submission should state clearly and concisely the results of your work and why they are significant. Representative data and/or figures that support your proposal are REQUIRED. The proposal must include the title of the presentation, and the name, affiliation, complete return address, telephone and telefax numbers, and e-mail address for each author. Submission should be by post or express mail (preferred). Telefax submissions will NOT be accepted. All submissions will be acknowledged. Visual aids for accepted proposals are required by September 12, 1998 for inclusion in the Presentation Handout at the meeting. A written presentation summary is due by December 1, 1998 for inclusion in the Final Report.

Eric S. Snyder, Technical Program Chair, 1998 IRW
Sandia Technologies
6003 Osuna Rd. NE
Albuquerque, NM 87109 USA
Tel: 505-872-0011
Fax: 505-872-0022
e-mail: SnyderST@aol.com  


Advance Registration should be made now to insure your space at the Workshop.


The Registration fee is US $900 for IEEE Members and US $950 for non-members, which includes: meals, lodging, and refreshments at the Stanford Sierra Camp; Presentation View Graphs (provided at the Meeting); and the 1998 IRW Final Report (published after the Meeting).


Nestled throughout the pines and cedars along the shoreline of Fallen Leaf Lake, a few miles from South Lake Tahoe, are clusters of 2 and 3 bedroom cabins furnished in the rustic style of an alpine resort. Each cabin cluster is equipped with shared bathroom facilities. All rooms have decks with magnificent views of Fallen Leaf Lake and surrounding Sierra peaks. 

The physical isolation of the location and the absence of distractions, such as in-room phones and television sets, encourages extensive interaction among the Workshop attendees.

Lodging is available for meeting attendees only. 


The JEDEC 14.2, Wafer Level Reliability Standards Committee, meeting will be held immediately after the Workshop at the Stanford Sierra Camp on Thursday afternoon and Friday morning. Members, alternates, and guests are welcome. The cost for the accommodations is $160.00, which includes Thursday night dinner and lodging and Friday breakfast and lunch. All attendees must leave the camp after lunch on Friday. If you have any questions or if you want to become a member of JC-14.2, please call the JEDEC office at (703) 907-7558.  


The Wafer Level Reliability Workshop was initiated in 1982 through the efforts of O. D. "Bud" Trapp, of Technology Associates, and the active support and encouragement of DARPA (Defense Advanced Research Projects Agency). This support continued for the first eight years of the Workshop and included active support and involvement of the Stanford University Integrated Circuits Laboratory and the University of California, Berkeley, Dept. of Electrical Engineering and Computer Sciences. After DARPA sponsorship ended, Bud Trapp continued the direction of the Workshop until 1991 after which time he requested that sponsorship and management be assumed by an appropriate professional association. The IEEE accepted this responsibility in 1992. In 1993, the name of the Workshop was changed to the Integrated Reliability Workshop. This change reflects the enlarged scope of the Workshop, the integrated nature of reliability in the manufacture of semiconductor products, and the need for a broader and a more comprehensive approach to reliability engineering.

The International Integrated Reliability Workshop is sponsored and managed by the IEEE Electron Device Society and the IEEE Reliability Society through the Board of Directors of the International Reliability Physics Symposium.