TUESDAY, October 13, 10:00 a.m. - 11:40 a.m
Session #1: Designing In Reliability (DIR) Harry Schafft, NIST, Chair

DIR-1

"Thermal Conductance of IC Interconnects Embedded in Dielectric," J.P. Gill, T.D. Sullivan, and D.L. Harmon of IBM Microelectronics, Essex Junction, VT

DIR-2

"Wafer Level Electromigration Applied to Advance Copper/Low k Dielectric Process Sequence Integration," Donald Pierce of Sandia Technologies, Albuquerque, NM; James Educato, Viren Rana and Dennis Yost of Applied Materials, Santa Clara, CA

DIR-3

"Wafer Level Monitoring and Process Optimization for Robust Via EM Reliability," T. Zhao, C. Shih, J. McCollum, F. Hawley, F. Issaq, B. Cronquist, R. Lambertson, E. Hamdy of Actel, Sunnyvale, CA; Z. Yang, C. Chern, M. Liao, G. Say, G. Koh, L. Chan, R. Sundaresan of Chartered Semiconductor Manufacturing, Singapore

DIR-4

"A Study of Stress Voiding Effect on AlSi Metal Bank Allowed Lifetime for a IC Foundry Fabs," K.P. Lin, C.D. Chang, K.S. Huang, S.L. Hsu of Taiwan Semiconductor Manufacturing Company Ltd., Hsin-Chu, Taiwan R.O.C.