1996 International




October 20-23, 1996

Stanford Sierra Camp, S. Lake Tahoe, CA U.S.A.



IEEE Electron Device Society & Rel Society



Workshop Experience

Major Technical Themes

Keynote Address

Discussion Groups


Open Poster Sessions

Special Interest Groups

Technical Program

JEDEC Committee 14.2 Meeting (Oct. 23-24)

Registration Form





Workshop Experience

You are cordially invited to participate in the

1996 Integrated Reliability Workshop. The Workshop

provides a unique forum for sharing new approaches

to achieve and maintain microelectronic component

reliability. The Workshop features presentations,

tutorials, open poster sessions, moderated discussion

group sessions, and special interest group (SIG) meetings.

All Workshop activities take place in a relaxed and

rustic setting that promotes an atmosphere of interactive

learning and knowledge sharing.

Major Technical Themes

Aggressive cost, reliability, and market entry demands are forcing

the semiconductor industry to consider alternatives to the

traditional and increasingly inadequate approach of testing-in-reliability

(e.g., burn-in, life test). In response to these concerns, the Workshop

is continuing to highlight the need for an integrated approach to ensure

product reliability, in which a detailed understanding of potential

failure mechanisms and their sources are proactively incorporated

into robust design and manufacturing practices. The four topical areas

for this year's Workshop reflect the scope of this approach and serve

as a framework for exploring solutions.

***Physics of the Failure***

Fundamental investigations into potential failure mechanisms,

their sources, and methods of activation.

***Reliability Test Structures***

Tools for investigating and monitoring failure mechanisms.

***Wafer Level Reliability***

In-line or end-of-line reliability measurements for manufacturing

control verification and early detection of specific reliability problems.

***Building-In Reliability***

A methodology for eliminating causes of product failure through

proactive reliability engineering integrated throughout all phases

of product conception, development, and manufacturing.


Does Building-In Reliability Imply

More or Less

Wafer-Level Reliability Testing?

Joe McPherson, Ph.D, TI Fellow

Texas Instruments, Inc., Dallas, Texas

Wafer-level reliability (WLR) testing continues to be an

important tool for implementing a building-in reliability (BIR)

strategy. The thrust of WLR testing has shifted, however,

from the back of the line (monitoring of outgoing reliability levels)

to the front of the line (margin testing during the development

and productization phase). The rapid nature of most WLR tests

permits the process engineer to evaluate the impact of process

variation and to obtain an "almost instantaneous" feedback as to

its reliability impact. Rapid reliability feedback is a key to

helping the process engineer to build reliability into the technology.

This is extremely important today when technologies are being developed

and introduced to fabs at a rapid rate.

Discussion Groups

A highlight of the Workshop is the evening discussion group program.

Attendees will have a choice of four topics on both Monday and

Tuesday evenings. The same four topics will be discussed for

90 minutes each night. This year's topics are:

***Wafer Level Techniques as a Quality and Reliability Tool***

Leaders: Don Pierce and Eric Snyder, Sandia Technologies

The large stresses used in wafer level reliability test techniques

yield data with test times orders of magnitude shorter than

conventional techniques. These fast tests have drawn much interest

throughout the industry, though there appears to be tremendous

variability in implementation, approach, and application.

In this discussion group, group participation will be used to scope

the degree of implementation of WLR across the industry, what new

requirements could be met by WLR and what advances in WLR techniques

are needed to meet those requirements.

***BIR Implementation Discussion Group***

Leaders: James Prendergast and John Steeves, Analog Devices

BIR is a proactive approach to reliability, where it must be

recognized that the end goal of a company is to produce reliable

product in a timely, cost-effective manner. This can be done

now only if reliability is incorporated into the design, process,

and assembly phases of product development. While we all, I think,

agree that this is the correct approach to adopt ...implementation

of BIR is not easy because it requires, among other things, rather

severe changes in attitude and in traditional working relationships.

You all, novices to experts, come to this discussion group to share

your experiences, data, questions, perspectives as we ...in lively,

interesting and entertaining discussions... seek to discover and to

describe paths of BIR implementation.

***Interconnect Reliability***

Leaders: Tim Sullivan, IBM and Shekhar Pramanick, AMD

Suggested topics for discussion:

*Can wafer level testing techniques provide valid and accurate

lifetime projection, or do current and temperature levels

fundamentally alter electromigration physics, kinetics or

failure localization?

*How do refractory layers affect lifetime?

*Can wafer level techniques be used to evaluate their effectiveness?

*Does stress voiding influence wafer level EM more or less than

conventional EM testing?

*Are thermal gradients more important in wafer level testing?

*Can results be invalidated by neighboring structures such as W studs?

***Thin Oxide Reliability***

Leaders: John Suehle, NIST and Raif Hijab, AMD

Suggested topics for discussion:

*What information do wafer level oxide evaluation tools

(Vramp, Qbd, etc.) provide?

*What's hot in new oxide evaluation methods, particularly

for very thin oxides?

*How useful are they for reliability prediction?

*What test conditions and breakdown criteria are applicable

for very thin oxides?

*What is the validity of oxide reliability models at high & low fields?

*What is the upper temperature limit for valid extrapolation

to lower temperatures?

*How is oxide thickness accurately determined from measurements

(CV, FN, etc.)?

*What corrections are needed for calculating the actual field across

the oxide?


In our continuing effort to enhance the value of the Workshop and to

strengthen the Technical Program, we are again offering two tutorials

on Sunday afternoon.


Predictive Wafer Level Reliability:

A New Archetype


Don Pierce and Eric Snyder

Sandia Technologies

Assuring IC reliability is becoming more of a challenge as device

geometries shrink, environments become more stressful and the

time-to-market becomes shorter. Traditional wafer level reliability

(WLR) approaches have emphasized test speed over quality of data with

the underlying assumption that WLR at best is a crude indicator of

process reliability. We believe that if sound physical principles

are followed, the quality of WLR data can be improved dramatically

and can yield results identical to those obtained using much slower

and more costly packaged-test approaches. This is a dramatic departure

from the conventional wisdom and is steeped in controversy, as is often

the case with the state-of-the-art.

We will describe how implementation of this new type of WLR helps

semiconductor manufacturers and users meet the challenge of assuring

IC reliability. This physics-based approach provides quantitative

data economically in a short period of time, supporting process monitoring,

rapid reliability qualification of processes/foundries and extraction of

key parameters that will be needed for future design for reliability tools.

This tutorial will show the approaches needed to maximize the quality of

WLR data using theory backed up with data. The technical examples will

demonstrate the features and utility of WLR when the test methodology

optimized for predictability and not just speed. This, the proper approach

to WLR, saves time and money over traditional WLR.


Effects of Mechanical Stresses,

Microstructure and Interconnect Structure

on Metallization Reliability


John Sanchez*, University of Michigan (*presenter)


Paul Besser, Advanced Micro Devices

It is well known that stresses, microstructure and the structure of

metallization interconnects controls the reliability of patterned

interconnects in integrated circuit devices. This tutorial will

review some of the fundamentals in each of these areas, and provide

a connection between fundamental understanding and applied interconnect

engineering issues for both development and manufacturing environments.

Actual examples which are useful for the design of more manufacturable

and more reliable interconnect systems will be presented.

Deposited metal films and patterned lines are often subjected to

large stresses and strains. The nature of these stress states, which is

determined by the film or line geometry, will be reviewed. The

metallurgical and geometrical factors which control the mechanical

behavior of films and lines are presented, as are the processes which

induce hillocks, sunken grains and voids.

The next part of this tutorial will focus on the microstructural

evolution of metal films and lines, and review these effects on

electromigration-induced failure mechanisms. The effects of line

grain size and textures on reliability will be presented, including

theoretical calculations, simulations and correlations with experimental


The effects of layering Al with refractory barriers on interconnect

microstructure and reliability will be discussed. Control of the Al

microstructure (grain size and texture) by the correct choice of Ti and/or

TiN layering schemes for improved performance, manufacturing reliability

and performance will be discussed. It will be shown that the Ti + Al

reaction can be controlled by the proper choice of Al-alloy.

Open Poster Sessions

The Technical Program will include two open poster sessions.

All attendees have the opportunity to present a poster to

communicate their ideas and results on a technical project or

issue. There is a place on the registration form to reserve a

poster display board (32" ´ 40" or 81 cm ´ 100 cm). Your work

should be in Landscape format on 8 1/2 ´ 11" or A4 paper with a

maximum of twelve pages. In addition, you are invited to submit a

one-page abstract of your poster presentation for inclusion in

the Workshop Final Report. This is a great opportunity for you

to share your work with your peers.

Special Interest Groups (SIG)

The SIG program at the Workshop has been very successful in

fostering collaborative work on important reliability issues

and we look forward to continuing growth and renewal in our

SIGs. The formation of SIGs is encouraged as a natural extension

of the Discussion Group sessions. Anyone interested in more information

about SIGs is encouraged to contact SIG Coordinator, David Kirchner at


JEDEC 14.2 Meeting

The JEDEC 14.2 Wafer Level Reliability Standards Committee meeting

will be held immediately after the workshop at the Stanford Sierra Camp

Wednesday afternoon and Thursday until noon. Members, alternates, and

guests are also welcome. Please use the workshop registration form to

register for the JEDEC meeting.

More Information

We expect an exciting workshop again this year. We look forward to

your active participation in the many Workshop activities and your

valuable contribution to the technical program. If you have any

questions, please contact me, James W. Miller, by phone, 512-933-7297,

or fax, ...7662, or e-mail: rvkg60@email.sps.mot.com, or

Cleston Messick, General Chair, at 801-562-7546, fax...7500,

email: CCRMSL@tevm2.nsc.com.


Complete and mail the enclosed registration form. Please register

early. We were completely sold out last year. Space at the Camp limits

the Workshop to roughly 120 attendees.

We look forward to seeing you at the '96 Workshop!


James W. Miller

Technical Program Chair