2002 IRPS TUTORIAL PROGRAM
Chair: Tom Moore, Omniprobe, Inc.
As increasing investments are made in VLSI technology and development, it becomes essential that semiconductor processes and IC designs have reliability issues addressed prior to volume manufacturing. Ideally, reliability issues would be addressed and corrected during the design process. This tutorial provides the motivation for understanding semiconductor reliability issues, a basic review of reliability wearout mechanisms, a discussion of how reliability mechanisms can be checked and corrected in the design phase, and how process technologies such as Cu interconnects and low-K dielectrics influence reliability design guidelines. This tutorial will provide the foundation to allow you to build technical depth in the areas of specific interest throughout the rest of the symposium.
An overview of past and present oxide reliability characterization techniques and degradation physics will be presented. This overview will provide a background in the physics, statistics, models, and characterization methodologies necessary for understanding the reliability issues present in current technology ultra-thin gate oxides.
This presentation will provide an understanding of the ESD phenomena and the impact on IC circuit reliability. In addition, it will provide an insight into the future reliability issues for ESD.
We will examine the three radiation mechanisms responsible for soft errors and see how these sources can be quantified and their impact predicted. We will consider scaling trends in soft error performance and conclude by touching on common design and process strategies used to reduce soft error rate.
What do soft errors look like at the data pins of memory components? We will show how this is influenced by the structure of the devices, and cover results of accelerated tests and system tests for soft errors. Finally the trend of decreasing SER for the last 8 generations of DRAMs is also shown.
This presentation describes accelerated radiation testing experiments performed to investigate cosmic ray soft errors in memory systems. A description of cosmic ray induced memory problems from single and multi-bit errors is presented as well as the implications of those problems on system design
Recent studies have shown that the core logic of microprocessors is becoming increasingly susceptible to single event upsets and can no longer be neglected. This talk analyzes the impact of technology scaling and internal logic design on the soft error rates at the device, circuit, and system levels.
Alpha particles from IC materials are known to cause SEU in semiconductor devices. Since 1978, the semiconductor industry has had to find accurate techniques for measuring these naturally occurring trace amounts of alpha emitting contaminants. This talk discusses some common metrology methods, with emphasis on gas flow proportional counters.
Alpha emission surface counting techniques are limited by analysis times and detection limits. Inovatia Laboratories has developed a method for the semiconductor industry that will achieve the equivalent of 0.002 cph/cm2 in 4 hours. The user may achieve lower detection limits by manipulating sample sizes and counting times.
The occurrence of soft errors in today's CMOS technology is at odds with the high availability requirements of server customers. This presentation will outline the design methodology and a variety of fault masking techniques that are in use in today's servers to eliminate the effect of soft errors.
With increasingly advanced process technology, the soft error (SER) susceptibility of ICs poses a formidable challenge to their reliability. This is especially true for mission critical applications. This talk will describe a systematic approach to help designers cope with SER using two basic steps: 1) SER estimation and 2) SER reduction techniques.
Server designers need to know the type and rate of errors that will occur in order to design systems that meet the reliability/accessibility/ serviceability requirements. A discussion of the needs of server designers and the design trade-offs that must be made to prevent cost or performance penalties will be presented.
Soft error vulnerability for memories is established. Now, the logic part of chips is just as vulnerable, receiving attention by relatively few. Protection of logic is different from memories. We will demonstrate radiation test results for a SPARC chip with and without protection demonstrating sensitivity to and protection from soft errors.
Energetic particles in space produce soft errors and other effects in microelectronics. Methods to deal with this include error detection and correction, power cycling, and operational methods. This paper discusses these techniques, including real examples where they have been applied, along with cases where unexpected responses have caused electronic malfunctions.
Techniques for mitigation of single-event upset, latchup, and gate rupture/burnout will be presented. Mitigation options include component-level technology solutions, hardened circuit designs, and fault-tolerant system architectures. Examples of each of these techniques will be given, and the impact of technology trends on the feasibility of mitigation solutions will be discussed.
Standard reliability testing is done using the time to failure test methodology. Over the error budget, the problems of this method and the influences of the inaccuracy of e.g. stress conditions and the influences of sample differences will be demonstrated. Optimisation of the "time to failure" methodology and alternative techniques and possibilities will be discussed.
New Phenomena in the Device Reliability Physics of Advanced Submicron CMOS Technologies (NBTI)
This tutorial will give an overview of some of the new reliability phenomena observed in MOSFET devices of advanced submicron CMOS technologies and their impact to reliability lifetime projections. Some focus will be given to Hot Carrier Reliability Phenomena such as e-e scattering, secondary impact ionization as well as parasitic drain series resistance effects in NMOSFET as well as hot hole damage in PMOSFET devices. In addition the role of Negative Bias Temperature Instabilites (NBTI) as technology limiter in the design of PMOSFET submicron devices will be discussed. The impact of these phenomena to DC and AC based circuit lifetime projections as well as methodologies will be given.
Electromigration (EM) has been a major interconnect reliability concern from the early days of integrated circuit technology. This tutorial will describe EM in the context of Al-based technology and lead into present day concerns and new techniques about assessing interconnect reliability, especially in the case of Cu dual-damascene interconnects. Some topics to be discussed will include the Blech effect, mass transport pathways, and early failure.
Assuring IC reliability is even more challenging today with new materials and higher than ever levels of material stress. Wafer Level Reliability (WLR) is one tool that can help meet this challenge. Traditional WLR approaches have emphasized test speed over quality of data. This tutorial will introduce Predictive WLR and show how proper attention to the underlying reliability physics can yield WLR that provides quantitative data similar to packaged-level tests in a much shorter time. This predictive WLR supports process monitoring, rapid qualification and development. We describe the theoretical approach needed to maximize the quality of WLR data with examples of Cu/low-k electromigration and vias, ultra-thin oxide breakdown, deep submicron hot-carriers, plasma damage and mobile ions. These technical examples show the features and utility of a WLR that is optimized for predictability and not just speed.
Defect Reliability Statistics with Redundancy Power and intrinsic wearout have begun to limit the effectiveness and increase the costs of burn-in for high-performance silicon processes. This tutorial covers approaches and models useful in controlling infant mortality today. Power management in burn-in, fault-tolerant chip design, population slicing, etc. will be discussed.
Silicon technology evolution continues at an increasing pace. The need for improved circuit performance and ever-higher levels of circuit integration necessitate aggressive feature size scaling and the introduction into the manufacturing environment of novel materials. In the process, existing materials are being pushed to their physical and electrical limits while the long-term implications of the use of newer materials are not fully understood. One of the major concerns for future technology development is the maintenance of the high level of reliability that the industry has attained. This course will provide an overview of the major silicon - related reliability issues for advanced semiconductor technologies. The emphasis of this course will be on the physical understanding of failure modes relevant to the advanced transistor structures and new materials used in the latest generations of silicon integrated circuit technology.
The implementation of Cu-based interconnect structures is the result of the development of novel processing schemes and the learning of
new paradigms for structure-processing relationships, as well the application of relevant portions of the existing Al-based interconnect
knowledge foundation. As an example, the challenging tight pitch metallization schemes for 130 nm generation technologies and beyond, require
novel damascene patterning of Cu-filled trenches filled by bottom-up electroplating. The stringent Cu diffusion barrier and electroplating
requirements dictate refractory metal and Cu "seed" layers, however experience learned during Al-based multilayer metallization development may be
applied to barrier metal/Cu interconnect process development. In addition, basic materials' properties and processing effects will also determine
the mechanisms controlling Cu interconnect reliability, although the degree to which individual mechanisms may vary since typical Cu
microstructures and mechanical properties vary from typical Al-based structures. This tutorial will describe the key factors that control Cu interconnect
reliability: interconnect microstructure and the dependence on processing schemes; mechanical stresses and the dependence on dielectric constraint
and thermal processing; and diffusional mechanisms that determine stress evolution, voiding, delamination and interconnect failure.
This tutorial addresses the unique application possibilities of Raman spectroscopy for microelectronics. After a short introduction on the
Raman spectroscopy theory, the instrumentation is explained, including spatial resolution and confocality. Next examples are given where
Raman spectroscopy is used for the study of composition, doping, crystallinity, phase, temperature and mechanical stress. These examples cover
different materials, such as Si, InSb, SiGe, AlGaAs, diamond, and silicides. The main focus of this tutorial will be on the use of Raman spectroscopy to
study local mechanical stress. Examples are given for stress introduced by isolation (LOCOS, shallow trench, deep trench) and silicidation,. But
also packaging related stress is discussed, such as near solder bumps are even in the whole packaged chip. This includes both one and
two-dimensional stress maps. Finally, examples are given where the technique was used to study stress in MEMS, such as membranes.
This tutorial will focus on the intrinsic and extrinsic defects in current and planned semiconductor package technologies that
require imaging techniques to fault isolate and identify failure mechanisms prior to destructive analysis. . The techniques that will be
discussed are x-ray radiography/topography, scanning acoustic microscopy, scanning squid microscopy, time domain reflectometry,
thermal and terahertz imaging. These tools and techniques will be discussed from the point of view of current capability and limitations
and the general direction needed for future capability that is consistent with semiconductor packaging trends.
This course will provide attendees with a basic working knowledge of how to design MEMS/MOEMS for reliability. The course will
concentrate on MEMS design, reliability physics, MEMS-specific fundamental reliability phenomena and failure mechanisms, and accelerated testing
protocols. Practical and useful examples from various arenas of MEMS application will be provided. LEARNING OUTCOMES This course will enable
Learn how to efficiently construct a MEMS reliability test plan to expand beyond qualification-based knowledge
Evaluate specific MEMS designs for reliability investigations
Understand the importance of fundamental models of MEMS failure mechanisms in designing accelerated testing strategies
Assess reliability test results to obtain truly robust MEMS designs.
INTENDED AUDIENCE Anyone who needs to learn how to design reliable MEMS. This course will be of value to those who either design their own MEMS or those who work directly or indirectly with MEMS designers. MEMS Materials, Fabrication, Packaging, Design, Reliability and Test engineers will benefit from this overview of MEMS Reliability physics.
A review on the reliability of analog/mixed signal technologies is provided with SiGe BiCMOS as an example. The forward and reverse mode reliability of SiGe HBTs are discussed as well as CMOS reliability focused on analog applications. Reliability issues for passive components such as capacitors, resistors, and inductors are also reviewed.
Numerous aspects of the GaAs MMIC must be considered to accurately determine its reliability. Various common failure mechanisms for
GaAs devices and methods of determining lifetime will be discussed. Example of accelerated life tests will be shown. The importance of proper
channel temperature evaluation will be explained.
First, we will discuss the different failure modes and mechanisms responsible for HBT degradation. Next, we will cover a physics-based model that qualitatively and quantitatively describes GaAs HBT degradation. Finally, we will discuss the key parameters that affect reliability, through a description of recent results on InGaP-emitter HBTs.