Trap Generation Phenomenon in Thin Dielectrics Under Electrical Stress

Aggressive device scaling calls for gate dielectrics with smaller effective oxide thickness and raises concerns about their reliability. So far, extensive research efforts to identify the key factor controlling degradation of SiO2 films have not yielded a comprehensive model, while our understanding of the high-k materials is even further away. This tutorial provides high-level overview/analysis of the conventional oxide degradation models and discusses an alternative mechanism for defect generation. Defect formation is considered at an atomic level as a multi-step phenomenon subsequently involving several physical and chemical processes. Applications to high-k dielectrics are discussed.

Gennadi Bersuker

Gennadi Bersuker completed his M.S. and Ph.D. in physics at the Leningrad State University and Kishinev State University (USSR). After graduation, he joined Moldavian Academy of Sciences and then worked at Leiden University (The Netherlands) and the University of Texas at Austin. Since 1994, he has been working at International SEMATECH on process induced charging damage, electrical characterization of Cu/low K interconnect, high K gate dielectrics and advanced CMOS process development.