Technical Program Abstracts

Stress-induced voiding can occur in Cu-based, deep-submicron, dual-damascene technologies where voids are formed under the via when the via connects to a wide metal lead below it. The voiding results from the supersatuation of vacancies that can occur due to grain growth when the Cu is not properly annealed prior to being fully constrained. The driving force for voiding is shown to be stress migration with a maximum in voiding rate observed at ~ 190 °C. A diffusional model is presented which clearly shows that the voiding mechanism is an issue primarily for vias to wide Cu leads. A thermomechanical stress exponent of 3.2 and a diffusional activation energy of 0.74 eV were determined for this stress-induced voiding mechanism.
4D.4 ELECTROMIGRATION STUDY OF CU/LOW K DUAL-DAMASCENE INTERCONNECTS—K.-D. Lee, X. Lu, E.T. Ogawa, H. Matsuhashi, V.A. Blaschke, R.Augur, SEMATECH, Austin, TX and P.S. Ho, Univ. of Tx, Austin, TX
Electromigration lifetime and failure mechanism have been studied for Cu/low k interconnects with SiLK and an inorganic porous ILD. The activation energies were 0.98 eV for SiLK and 0.80 eV for the porous low k, similar to that of oxide but the lifetimes were 5x and 10x lower, respectively. FIB revealed a distinct failure mode due to Cu extrusion at the anode under the cap layer. These results can be attributed to the thermomechanical properties and interfacial adhesion of the low k structure.
4D.5 ELECTROMIGRATION OF CU AND AL USING WAFER LEVEL ISOTHERMAL TECHNIQUE—T.C. Lee, D.M. Tibel, and T.D. Sullivan, IBM, Essex Jct., VT
Wafer level electromigraton behavior of copper and aluminum using isothermal technique is reported. Lifetime, shape factor, and activation energy are evaluated as a function of stress temperature as well as of line width. Temperature dependence of the embedded 2D thermal behavior is also modeled via the initial stress current and the initial resistance.
4D.6 MODELING AND ANALYSIS OF VIA HOT SPOTS AND IMPLICATIONS FOR ULSI INTERCONNECT RELIABILITY—S. Im, K. Banerjee, and K.E. Goodson, Stanford Univ., Stanford, CA
In this paper, a new analytical model to evaluate via hot spots has been derived and compared with numerical simulations. It has been shown that hot spot locations and resultant temperature fields of interconnect/via structures are strongly coupled with structural and material parameters of vias. Hence, the development of metrology for hot spots will alleviate thermally-induced interconnect reliability issues in advanced integrated systems.
Thursday, April 11, 8:00 a.m., location Landmark A-B
5. PROCESS INDUCED DAMAGE
Co-Chairs: Tomasz Brozek, PDF Solutions and
Kin P. Cheung, Rutgers University
5.1 (Invited) USE OF EEPROM-BASED SENSORS IN INVESTIGATING PHYSICAL MECHANISMS RESPONSIBLE FOR CHARGING DAMAGE—W. Lukaszek, Wafer Charging Monitors, Woodside, CA
This presentation provides a review of charging phenomena observed in semiconductor manufacturing process equipment during the last decade, using material collected in a variety of IC processes. Both well-understood and anomalous phenomena will be illustrated with examples obtained with EEPROM-based (CHARM-2) sensors.
5.2 INFLUENCE OF PLASMA EDGE DAMAGE ON ERASE CHARACTERISTICS OF NOR FLASH EEPROM USING CHANNEL ERASE METHOD—D.-K. Lee, W.H. Lee, Y.-H. Na, K.-S. Kim, K.-O. Ahn, K.-D. Suh, Samsung Electronics, Yongin, Korea, and Y. Roh, Sungkyunkwan Univ., Suwon, Korea
Plasma processing of the stack gate may significantly impact operation of NVM memory and its reliability. This paper discusses effect of defects generated near tunneling oxide edge on erase characteristics of NOR Flash EEPROM. It is shown how optimization of the plasma etching process and choice of appropriate operating condition allows minimizing the impact of the defects.
5.3 ENHANCED PLASMA CHARGING DAMAGE DUE TO AC CHARGING EFFECT—Y. Jin, W.Y. Teo, Y.T. Hou, F.H. Gn, H.F. Lim, Z.Y. Han, and M.F. Li, Chartered Semiconductor Mfg., Singapore
Plasma charging damage from HDP IMD deposition process was found to be drastically enhanced as metal antenna is placed at higher interconnect level. Such charging damage enhancement is ascribed to AC charging effect. A modified charge sharing model is proposed to interpret such effect.
5.4 THE INFLUENCE OF IMD BAKE PROCESS ON BURIED CHANNEL PMOS HOT CARRIER RELIABILITY OF ADVANCED DRAM—S.J. Ahn, J.K. Lee, G.T. Jung, C.H. Cho, Y.S. Hwang, D.W. Shin, H.S. Jeong, and K. Kim, Samsung Electronics, Yongin, Korea
In this work influence of the SOG deposition with two kinds of curing process on the hot carrier reliability of buried channel (BC) PMOSFET is investigated. It was found that the vacuum bake increases the effective negative charges in the trench sidewall oxide and degrades p+ active isolation and pMOSFET hot carrier reliability.
5.5 IMPACT OF FOCUSED ION BEAM ASSISTED FRONT END PROCESSING ON N-MOSFET DEGRADATION—A. Lugstein, W. Brezna, and E. Bertagnolli, Vienna Univ. of Technology, Vienna, Austria
Impact of ion beam related damage on device degradation is quantified by in-situ electrical sensing of n-MOSFET during focused ion beam exposure. Apart from charging effects progressive device degradation is observed when long-range damage cascades extent into the channel region. The damage is attributed to channel mobility decrease and is described by a semi-empirical mobility model.
Thursday, April 11, 10:30 a.m., location Landmark A-B
PANEL DISCUSSION:
PRODUCT QUALIFICATION IN THE 21^st CENTURY
Thursday, April 11, 1:35 p.m., location Landmark A-B
SPECIAL TOPIC:
GERMICIDAL IRRADIATION OF THE US MAIL:
CAN ICs SURVIVE WHILE BACTERIA PERISH?
THE EFFECTS OF TOTAL IONIZING DOSE IRRADIATION ON CMOS TECHNOLOGY AND THE USE OF DESIGN TECHNIQUES TO MITIGATE TOTAL DOSE EFFECTS—R.C. Lacoe, The Aerospace Corporation, Los Angeles, CA
The effects of total ionize dose irradiation such as gamma- and x-rays as well as energetic electrons and protons on CMOS performance, at the single device level and at the circuit level, will be described. Data will be presented on the intrinsic total dose hardness of various CMOS processes, which indicates an increase in total dose hardness as CMOS technology is scaled. Design techniques and their effacacy in mitigating against total dose effects will also be described.
EFFECTS OF E-BEAM MAIL SANTIZING PROCESS ON COMMERCIAL ELECTRONICS— F.W. Sexton, P.E. Dodd, M.R. Shaneyfelt, and J.R. Schwank, Sandia National Laboratories, Albuquerque, NM
Following the tragic terrorist attacks of September 11th, 2001, and the subsequent anthrax bio-terrorism attacks, the United States Postal Service has instituted a process to sanitize mail passing through key mail handling centers. The process is based on the use of high doses of ionizing radiation to kill any anthrax spores that may be present. Electronics are among a wide group of items that are routinely sent through the mail and are known to be sensitive to ionizing radiation. This talk will summarize the procedure now used by the USPS in the context of the sensitivity of commercial electronics to ionizing radiation. Proposed alternate processes to authenticate mail originators to mitigate the need for irradiation will also be discussed.
FILTER OPTIMIZATION FOR X-RAY INSPECTION OF SURFACE-MOUNTED ICs—R.C. Blish, II, S.X. Li and D. Lehtonen, AMD, Sunnyvale, CA
A thin Zn filter (~20 um) and relatively low X-ray tube voltage (~45 KV) is recommended for X-ray inspection of surface-mounted device solder joints on printed wiring boards (PWB). An optimal filter minimizes the Si dose that could result in cumulative damage to sensitive IC circuit nodes, yet provides good contrast for metals such as Cu traces on PWB and device solder balls. While we expect orders of magnitude Si dose reductions when effective filters are inserted, a properly chosen filter should not attenuate the portion of the white X-ray spectrum required to image Cu, Sn and Pb (solder balls). Some X-ray inspection suppliers can achieve a Si dose of as little as 0.060 Rads; while other X-ray inspection suppliers, not yet optimized for minimum dose, may use as much as four orders of magnitude more dose. We used Thermo Luminescent Detectors (TLDs) to measure the X-ray dose that IC product shipments would encounter during a shipping process (personal baggage or cargo) as minimal (£0.050 Rads).
Thursday, April 11, 2:50 p.m., location Landmark A-B
6. DIELECTRICS II
Co-Chairs: M. Ashraful Alam, Agere Systems and Eric M. Vogel, NIST
6.1 IMAGING BREAKDOWN SPOTS IN SiO₂ FILMS AND MOS DEVICES WITH A CONDUCTIVE ATOMIC FORCE MICROSCOPE—M. Porti, M.C. Blüm, M. Nafria, and X. Aymerich, Universitat Autònoma de Barcelona, Bellaterra, Spain
SiO₂ breakdown is investigated on bare thin oxide films using a conductive atomic force microscope. The results show that the breakdown of a spot affects the dielectric strength of the surrounding area. Moreover, for the first time, breakdown spots in standard MOS devices are electrically imaged at the nano-scale.
6.2 ANALYSIS OF EXPONENTIAL DECAY TRANSIENT CURRENT IN MOS CAPACITORS—R. Yamada, Hitachi Ltd., Richmond, CA, and J. Yugami, Hitachi Ltd., Tokyo, Japan



	Technical Program Tuesday, April 9, 8:00 a.m., location Landmark A-B SYMPOSIUM OPENING: William R. Tonti Symposium General Chair Bernie M. Pietrucha, Technical Program Chair Keynote: —Bernard S. Meyerson, IBM Vice President, Communication, Research & Development Center. Bernie Meyerson's presentation will put into focus the issues and challenges associated with technologies now operating at frequencies never anticipated, even in the recent past. With device performance above 200 GHz, and circuit performance approaching 100 GHz, associated current loads on semiconductor and metal systems are becoming extraordinary. Similarly, new challenges emerge in the form of decreasing "breakdown" voltages for high speed devices, and new loss mechanisms for passive devices as radiative effects become dominant at such high frequencies. The Keynote presentation will include an overview of leading edge high performance technologies, and address the aforementioned issues in the context of how they impact the limits of where a given technology may be applied. Tuesday, April 9, 8:50 a.m., location Landmark A-B 1. NON VOLATILE MEMORY Co-Chairs: Fred G. Kuper, Philips and Neal R. Mielke, Intel 1.1 LOCALIZATION OF SILC IN FLASH MEMORIES AFTER PROGRAM/ERASE CYCLING—D. Ielmini, Politecnico di Milano, Milano, Italy, A.S. Spinelli, Università degli Studi dell'Insubria, Como, Italy, A.L. Lacaita, R. Leone, Politecnico di Milano, Milano, Italy, and A. Visconti, STMicroelectronics, Agrate Brianza, Italy A new technique for characterizing the SILC position in scaled memories indicates that 85% of SILC spots are near the drain. This result suggests that CHE programming, and not just Fowler-Nordheim erase, is responsible for the oxide damage. This method allows for optimization of P/E operation to maximize oxide reliability. 1.2 A NEW RELIABILITY MODEL FOR POST-CYCLING CHARGE RETENTION OF FLASH MEMORIES—H.P. Belgal, N. Righos, I. Kalastirsky, Intel, Folsom, CA, J. Peterson, Intel, Sacramento, CA, R. Shiner, formerly with Intel, Fair Oaks, CA, and N.R. Mielke, Intel, Santa Clara, CA This paper presents a reliability model for Flash SILC, with an excellent fit to multi-year bake data from five technology generations. The model accounts for dependence on field, time, temperature, cycles, cycling conditions, and oxide thickness. Optimized design and processing is demonstrated to reduce the effect to very low levels. 1.3 STATISTICAL MODELING OF THE PROGRAM/ERASE CYCLING ACCELERATION OF LOW TEMPERATURE DATA RETENTION IN FLOATING GATE NONVOLATILE MEMORIES—A. Hoefler, J.M. Higman, T.S. Harp, and P.J. Kuhn, Motorola, Austin, TX Cycling acceleration of anomalous SILC in floating gate non-volatile memories is reported over a range from 10 to 10⁵ program/erase cycles. Application of a statistical model shows that the leakage mechanism is independent of cycling. Leakage rate increases strongly from 10 to 10³ cycles, but the cycling effect saturates at 10⁵ cycles. 1.4 PHYSICAL DESCRIPTION OF ANOMALOUS CHARGE LOSS OF FLOATING GATE BASED NVMS AND IDENTIFICATION OF ITS DOMINANT PARAMETER—F. Schuler, R. Degraeve, P. Hendrickx, and D. Wellekens, IMEC, Leuven, Belgium We introduce a 3-dimensional physical conduction model to describe anomalous charge loss in non-volatile memories considering phonon assistance and discrete energy levels in potential wells. We identify the trap-trap-distance as the dominant parameter. This justifies the use of the percolation model to predict anomalous charge loss distributions. 1.5 CAUSE OF DATA RETENTION LOSS IN NITRIDE-BASED LOCALIZED TRAPPING STORAGE FLASH MEMORY CELLS—W.J. Tsai, S.H. Gu^#, N.K. Zous^#, C.C. Yeh, C.C. Liu, C.H. Chen, T. Wang^#, S. Pan, and C.Y. Lu, Macronix International Co., Hsin-Chu, Taiwan ^# National Chiao-Tung Univ., Hsin-Chu, Taiwan This paper investigates data loss mechanisms in P/E-cycled SONOS-type memory cells with localized trapping storage. The dominant mechanism in programmed cells is found to be leakage via oxide traps rather than electron lateral migration. Smaller V_t shifts in erased cells are attributed to hole detrapping and migration. 1.6 EMPIRICAL MODEL FOR FATIGUE OF PZT FERROELECTRIC MEMORIES—J. Rodriguez, J.W. McPherson, T. Moise, S. Summerfelt, S. Aggarwal, K.R. Udayakumar, C. Dunn, Texas Instruments, Dallas, TX, and S. Gilbert, Agilent Technologies, Palo Alto, CA Fatigue was investigated for sub-100nm ferroelectric PZT films. No polarization degradation occurs up to an incubation period, CTF, ~10⁸ cycles. CTF has process dependence but little voltage/temperature dependence. Beyond CTF*, fatigue shows exponential field dependence and weak temperature dependence. A novel field-accelerated lifetime model is presented. 1.7 DIELECTRICS: ESREF Best Paper (Invited) Failures in ultrathin oxides: Stored energy or carrier energy driven?—S. Bruyère, F. Monsieur, D. Roy, and E. Vincent, STMicroelectronics, Crolles France and G. Ghibaudo, LPCS/ENSERG, Grenoble, France Oxide failure manifestation is reported to be even softer as the oxide thickness scales downwards the SiO₂ limits. In this context, this paper gives a useful clarification between quasi-breakdown and breakdown phenomena occurring in ultrathin oxides. It is demonstrated that two failure modes, characterized by noise occurrence and current increase take place: one called quasi-breakdown, which failure site may be aged up to a stable stage, generating a leakage current significantly smaller than the classical hard breakdown and a second, the breakdown, which becomes more progressive with the oxide thickness reduction. Moreover, physical reasons explaining these softer behaviors are discussed and it is shown that the energy stored in the capacitor only impact the progressiveness of the failure site aging. On the contrary, the carrier energy at the anode drives the failure and can conduct to one or the other failure mode. Tuesday, April 9, 2:00 p.m., location Landmark A-B 2A DIELECTRICS I Co-Chairs: M. Ashraful Alam, Agere Systems and Eric M. Vogel, NIST 2A.1 A THOROUGH INVESTIGATION OF PROGRESSIVE BREAKDOWN IN ULTRA-THIN OXIDES: PHYSICAL UNDERSTANDING AND APPLICATION FOR INDUSTRIAL RELIABILITY ASSESSMENT—F. Monsieur, E. Vincent, D. Roy, S. Bruyere, STMicroelectronics, Crolles, France, G. Pananakakis, G. Ghibaudo, LPCS/ENSERG, Grenoble, France For oxide thickness below 25 Å, the breakdown path is no longer hard and there is no clear definition of device failure. In this work, the progressiveness of the breakdown is studied with respect to the stress parameters. The results may allow for the relaxation of reliability criterion, particularly in the case when physical failure (first event) does not lead to IC failure.



	2A.2 LOCATION AND HARDNESS OF THE OXIDE BREAKDOWN IN SHORT CHANNEL n- AND p-MOSFETS—F. Crupi, Universitá degli Studi di Messina, Messina, Italy, B. Kaczer, R. Degraeve, A. De Keersgieter, and G. Groeseneken, IMEC, Leuven, Belgium The location and the hardness of the oxide breakdown in short-channel n- and p-MOSFETs stressed at high voltages in inversion and in accumulation are investigated. In all cases, it is shown that the breakdown location is uniformly distributed along the total channel length and that the hardest circuit-killing oxide breakdowns occur in the case of nMOSFETs stressed in inversion. 2A.3 POLARITY DEPENDENT OXIDE BREAKDOWN OF NFET STRUCTURES FOR ULTRA-THIN GATE OXIDE — IS GATE VOLTAGE THE ONLY CONTROLLING VARIABLE FOR ULTRA-THIN OXIDE BREAKDOWN?—E. Wu, W. Lai, IBM, Essex Jct., VT, M. Khare, IBM, Hopewell Jct., NY, L.K. Han, IBM (now with TSMC), Hopewell Jct., NY, J. McKenna, formerly with IBM, Hopewell Jct., NY, D. Harmon, and A. Strong, IBM, Essex Jct., VT A systematic and detailed investigation of polarity dependent oxide breakdown for ultra-thin gate oxides is reported. Charge to breakdown (Q_bd) was found to be consistently lower for NFET accumulation than that of NFET inversion while time-to-breakdown (T_bd) shows a crossover behavior as oxide thickness is reduced. The work provides a unified picture and self-consistent account of various conflicting experimental results reported on polarity-dependent breakdown in the literature. 2A.4 GATE OXIDE RELIABILITY OF DRAIN-SIDE STRESSES COMPARED TO GATE STRESSES—N.A. Dumin, K. Liu, S.-H. Yang, Texas Instruments, Dallas, TX The differences between gate oxide breakdown of conventional gate stresses and gate oxide breakdown of drain-side stresses are investigated. For the same stress conditions, drain stresses are shown to have higher breakdown voltages and longer lifetimes. Therefore, the voltage limits predicted by conventional gate stress models may underestimate the maximum allowable supply. Tuesday, April 9, 4:05 p.m., location Landmark A-B 2B HOT CARRIERS Co-Chairs: Giuseppe La Rosa, IBM and Janet Wang, Transmeta 2B.1 NBT-INDUCED HOT CARRIER (HC) EFFECT: POSITIVE FEEDBACK MECHANISM IN p-MOSFET'S DEGRADATION—H. Aono, E. Murakami, K. Okuyama, K. Makabe, K. Kuroda, K. Watanabe, H. Ozaki, K. Yanagisawa, K. Kubota, and Y. Ohji, Hitachi, Tokyo, Japan We demonstrate a new mode of HC degradation of p-MOSFET's for the first time, which is enhanced by NBT stress. This is positive feedback HC degradation caused by positive fixed oxide charges. It is also shown that this new degradation can be suppressed by halo design. 2B.2 A DRAIN AVALANCHE HOT CARRIER LIFETIME MODEL FOR n- AND p-CHANNEL MOSFETs—N. Koike and K. Tatsuuma, Matsushita Electric Industrial Co., Kyoto, Japan A drain avalanche hot carrier lifetime model t(I_d / W )² µ (I_sub / I_d )^- m has been proposed. The model is based on the mechanism of interface trap generation caused by recombination of hot electrons and hot holes, which causes the exponent of I_d / W to be 2. The model has been confirmed experimentally for n- and p-channel MOSFET's. 2B.3 EXCESS HOT-CARRIER CURRENTS IN SOI MOSFETs AND ITS IMPLICATIONS—P. Su, UC Berkeley, Berkeley, CA, K. Goto, T. Sugii, Fujitsu Lab Ltd., Atsugi, Japan, and C. Hu, UC Berkeley, Berkeley, CA Excess hot-carrier currents in SOI-MOSFETs are caused by self-heating. Self-heating-free I_SUB data should be used for dynamic-lifetime-extrapolation due to long thermal time-constant. The underlying mechanism- increased impact-ionization with temperature at low drain-bias is studied experimentally from the angle of thermal activation energy. The driving force of impact-ionization is changing from electric-field to lattice-temperature as the power-supply-voltage is scaled down. 2B.4 EFFECTS OF HOT-CARRIER STRESS ON THE RF PERFORMANCE OF 0.18 µm TECHNOLOGY NMOSFETs AND CIRCUITS—S. Naseh, M.J. Deen, and O. Marinov, McMaster Univ., Hamilton, Canada The effects of DC hot-carrier stress on DC and RF performance of submicron LDD NMOSFETs are investigated. Using the device's small signal model, it is shown that the unity current- gain frequency f_T decreases as a result of both decrease in transconductance g_m of the transistor, and increase in gate-source capacitance C_gs with stress time. Based on the hot carriers effects on the transistor, these effects on the performance of a low noise amplifier (LNA) is studied. Power gain, input matching and stability of the LNA are degraded mostly due to degradation of g_m and output conductance g_ds. 2B.5 HOT CARRIER RELIABILITY OF N-LDMOS TRANSISTOR ARRAYS FOR POWER BiCMOS APPLICATIONS—D.J. Brisbin, A. Strachan, and P. Chaparala, National Semiconductor, Santa Clara, CA Today's handheld appliances often require high performance power management control devices in the 20-30 V range. The n-channel lateral DMOS (N-LDMOS) has been a common choice for the driver transistor. Due to the high N-LDMOS drain voltages hot carrier (HC) degradation is potentially an important reliability concern. This paper focuses on HC test methodology and geometry effects in N-LDMOS transistor arrays. This paper differs from previous work in that it discusses for the first time the HC performance of N-LDMOS transistor arrays rather than discrete devices and describes an N-LDMOS HC failure mode not yet addressed in the literature. Tuesday, April 9, 2:00 p.m., location Landmark C-D 2C MEMS Co-Chairs: Danelle M. Tanner, Sandia National Labs and Michael R. Douglass, Texas Instruments 2C.1(Invited) RF MEMS Switches and Applications—H.S. Newman, Naval Research Laboratory, Washington, DC RF MEMS devices are small mechanical devices fabricated by photolithographic processes which can be used for simple signal processing functions (transmission, control, and tuning) in RF and microwave frequency circuits. The most common RF MEMS control component is the microwave transmission line switch, currently under development for those applications which benefit from the device's low insertion loss and high linearity. This paper will discuss the operation of RF MEMS switches and how they may be inserted into microwave circuitry to best advantage.



	2C.2 (Invited) Techniques for Reliability Analysis of MEMS RF Switch—J. DeNatale, Rockwell Scientific, Thousand Oaks, CA MEMS switch technology represents a key enabling element for advanced RF systems. These devices provide extremely low loss, high linearity, and broad bandwidth relative to traditional semiconductor switches. The primary impediment to fully realizing these benefits in deployed systems is their reliability under high cycle numbers. Due to their low force actuation and multi-physics operation, the reliability of MEMS contact switches may be impacted by a broad range of different mechanisms. Thus, a key component of the reliability improvement process is the separation and identification of reliability-limiting processes. A number of experimental methods have been developed to support these determinations, and their application will be discussed. 2C.3 DIGITAL MICROMIRROR DEVICE™ (DMD™) HINGE MEMORY LIFETIME RELIABILITY MODELING—A.B. Sontheimer, Texas Instruments, Plano, TX This paper provides a brief description of the DMD, the parametrics observed in accelerated life tests, and the empirical reliability models derived from the testing. The paper demonstrates that the same methodology employed to model semiconductor reliability may successfully be applied to a MEMS device. 2C.4 PIN-JOINT DESIGN EFFECT ON THE RELIABILITY OF A POLYSILICON MICROENGINE—D.M. Tanner, J.A. Walraven, S.S. Mani, and S.E. Swanson, Sandia National Labs, Albuquerque, NM Reliability of surface-micromachined microengines is shown to be dependent on the pin joint design, which connects the electrostatic actuation to the rotating gear. Surprisingly, the design that minimizes contact area had a detrimental effect on the reliability, demonstrating how small design changes can cause a big impact on MEMS reliability. Tuesday, April 9, 4:05 p.m., location Landmark C-D 2D ASSEMBLY/PACKAGING Co-Chairs: Thomas M. Moore, Omniprobe, Inc. and S. Sidharth, AMD 2D.2 (Invited) PRODUCT-SPECIFIC `MOISTURE LEVELS': A CONCEPTUAL FRAMEWORK—R.C. Blish II, and S. Sidharth, AMD, Sunnyvale, CA An improved schedule to evaluate SMT popcorn jeopardy based on physics of moisture absorption is proposed. Key features are: each lettered Level implies a certain performance irrespective of package thickness (i. e., no penalty for thin packages); each Level has a 3-fold different moisture concentration at the molding compound/chip or molding compound/leadframe interface (i.e. uniform discrimination between Levels); the time required for preconditioning is substantially reduced from current practice. 2D.3 (Invited) HERMETICITY ISSUES IN MEMS PACKAGING—S.J. Jacobs, J.J. Malone, L.K. Magel, and S.A. Miller, Texas Instruments DLP™ Products, Dallas, TX Exposure of operating MEMS structures to atmospheric gasses may have deleterious effects on device performance. Here we consider from a phenomenological point of view the effects that moisture has on both short- and long-term performance characteristics of Texas Instruments' Digital Micromirror Device™ (DMD). As an array of up to 1.3 million mirrors, a single DMD provides a wealth of statistical information. The detection sensitivity of our test methods (mirror-by-mirror) provides significant insight into the global and local effects of water on device operation. 2D.4 (Invited) PROBING AND WIRE BONDING OF ALUMINUM CAPPED COPPER PADS —G. Hotchkiss, J. Aronoff, J. Broz, C. Hartfield, R. James, L. Stark, W. Subido, V. Sundararaman, and H. Test, Texas Instruments, Dallas, Texas Results are presented of an experimental study that compares wire-bonding characteristics of probed aluminum capped and etched aluminum bond pads. Wafers were probed multiple times to generate pads with measured damage ranging from 10-45% of total pad area. Analyses on bonded units include percent of Au-Al intermetallics formed, ball shear, wire pull, and underlying pad damage. The paper will highlight the differences found between the two methodologies and recommend basic changes that will enhance the assembly process of Al-capped copper bond pads. 2D.5 ACCELERATED RELIABILITY - THERMAL AND MECHANICAL FATIGUE SOLDER JOINTS METHODOLOGIES—N.E. Strifas, C. Vaughan, NAVSEA, Dahlgren, VA, M. Ruzzene, Catholic Univ., Washington, DC A generalized finite element analysis approach is presented for estimating the reliability of solder joints for surface mount devices based on the viscoplastic constitutive law for solder joint response and the crack growth rate model for solder joint fatigue. An accelerated life prediction model is developed for eutectic Sn-Pb solder joints assuming a Weibull two-parameter failure distribution. Tuesday, April 9, 7:00 p.m., Union Station DEVICE DIELECTRICS POSTERS Co-Chairs: M. Ashraful Alam, Agere Systems and Eric M. Vogel, NIST DD.1 STRESS INDUCED LEAKAGE CURRENT AND BULK OXIDE TRAPPING: TEMPERATURE EVOLUTION—G. Ghidini, A. Sebastiani, and D. Brazzelli, STMicroelectronics, Agrate Brianza, Italy Aim of this work is the study of the correlation between SILC and bulk trapped charge by investigating their high temperature annealing kinetics. For the first time a linear correlation between them has been found even during annealing procedures, showing the same activation energy (1.1eV). Furthermore, the full SILC recovery does not correspond to the full recovery of the bulk trapped charge, suggesting that the recovery of SILC is obtained by repairing a critical trap in the multiple trap path. The nitridation technology simply reduces the amount of degradation, without changing the physical defect associated. DD.2 ATOMISTIC MODEL FOR E' CENTER GENERATION DURING ELECTRICAL STRESS—G. Bersuker, International SEMATECH, Austin, TX, Anatoli Korkin, Motorola, Mesa, AZ, Yongjoo Jeon, and Howard R. Huff, International SEMATECH, Austin, TX A model is proposed which addresses the effects of the oxide electric field and anode bias as well as discusses the role of hydrogen in the trap generation process. The oxide wear-out phenomenon is considered as a multi-step process initiated by the capture of injected electrons by localized states in SiO₂. The captured electron significantly weakens the corresponding Si-O bond, which becomes unstable with respect to the applied electric field and temperature. The hydrogen presented in the oxide (due to anode hydrogen release process) prevents restoration of the broken bond that leads to the generation of a neutral E' center. The model describes the charge-to-breakdown dependence on the electron fluence and energy, electric field, temperature and oxide thickness.

DD.3 CHARGING EFFECTS ON RELIABILITY OF HfO₂ DEVICES WITH POLYSILICON GATE ELECTRODE—K. Onishi, C.S. Kang, R. Choi, H.-J. Cho, S. Gopalan, R. Nieh, S. Krishnan, and J.C. Lee, The Univ. of Texas, Austin, Texas.

Time dependent dielectric breakdown and bias temperature instability of HfO₂ devices with polysilicon gate electrode have been studied. Both N and PMOS capacitors have large enough TDDB, whereas PMOS capacitors show gradual increase in the leakage current. HfO₂ PMOSFET's without nitridation have sufficient immunity against negative bias temperature instability. Bias temperature instability for NMOS can be a potential scaling limit for HfO₂.

DD.4 MODELING KINETICS OF GATE OXIDE RELIABILITY USING STRETCHED EXPONENTS—M.S. Krishnan and V. Kol'dyaev, PDF Solutions, San Jose, CA

In this work, the use of stretched exponents to model the kinetics of gate oxide reliability is explored. Stretched exponents are better able to capture the underlying kinetics of degradation compared to other phenomenological models in literature such as the logarithmic and power law models. With the use of a single stretched exponential function, multiple stages and mechanisms of oxide degradation behavior such as hot-carrier physics and negative bias-temperature instability (NBTI) is modeled.

Tuesday, April 9, 7:00 p.m., Union Station

DEVICE & PROCESS POSTERS

Co-Chairs: Prasad Chaparala, National Semiconductor and
Srikanth Krishnan, Texas Instruments

DP.1 ELECTROTHERMAL SIMULATION OF SiC GTO THYRISTOR WITH A TURN-OFF SNUBBER IN A CLAMPED INDUCTIVE LOAD CIRCUIT—P.B. Shah, U.S. Army Research Lab, Adelphi, MD

Two dimensional electrothermal simulations were made to investigate how to increase the reliability of SiC GTO thyristors used in power conversion circuits for electric motor drive by optimizing the region thickness, concentrations, and contact layout. Accurate high-temperature models to represent 4H-SiC were developed. The influence of the clamped inductive load and turn-off snubber will be discussed.

DP.2 TEMPERATURE DEPENDENCE OF R_on, _sp IN SILICON CARBIDE AND GaAs SCHOTTKY DIODE—J. Luo, K.J. Chung, H. Huang and J.B. Bernstein, Univ. of Maryland, College Park, MD

SiC has been widely accepted as a superior alternative to GaAs in power device applications because it has much higher electric breakdown field, saturated electron drift velocity and thermal conductivity. In this work, the electrical performance and reliability of SiC Schottky diodes (SD) are evaluated and compared to commercially available GaAs SDs. Accelerated life tests (ACT) and high temperature device characterization have been performed. The specific on resistance R_on, _sp increased with temperature according to T^0.72 dependence for GaAs, T^1.89 for SiC, which is very close to the result reported by T. Urushidani etc. Based on Baliga's figure-of-merit (BFOM) model, the I-V characterization data were normalized to the blocking voltage. The result shows that under higher operating temperatures (>260°C) the GaAs devices have lower R_on,sp than SiC. This could be due to the high mobility and weaker temperature dependence of GaAs, thus, it may be preferable to use GaAs over SiC for high frequency power device applications under very high temperature condition.

Tuesday, April 9, 7:00 p.m., Union Station

HOT CARRIERS POSTERS

Co-Chairs: Giuseppe La Rosa, IBM and Janet Wang, Transmeta

HC.1 SUB-0.25 µm MOSFET IMPACT IONIZATION AND PHOTON GENERATION DYNAMICS BASED ON HIGH-RESOLUTION PHOTO-EMISSION SPECTRUM ANALYSIS—R. Muniandy, Intel Philippines

High-resolution photon emission spectrometry has been employed to study impact ionization and photon generation dynamics in deep sub-micron MOSFET. A physical impact ionization indirect band-gap recombination model, which is in good agreement with the broadband spectrum properties, has been developed. Abrupt change to photon emission spectrum profile at 1.8eV has been attributed to energy - momentum conservation requirements during impact ionization.

HC.2 HOT CARRIER RELIABILITY OF n-MOSFET WITH ULTRA-THIN HfO₂ GATE DIELECTRIC AND POLY-SI GATE—Q. Lu, H.Takeuchi, R. Lin, T.-J. King, C. Hu, UC Berkeley, Berkeley, CA, K. Onishi, R.Choi, C.-S. Kang and J.C. Lee, The Univ. of Texas, Austin, TX



	Hot carrier reliability of n-channel MOSFETs with 11 Å EOT HfO₂ gate dielectric and poly-Si gate was studied. Under peak I_SUB stress conditions, n-FETs with HfO₂ gate dielectric show longer lifetime than SiO₂ n-FETs for the same stress substrate current. The major device degradation mechanism is likely interface trap generation. Tuesday, April 9, 7:00 p.m., Union Station INTERCONNECTS POSTERS Co-Chairs: Michael J. Dion, Intersil and James A. Walls, Motorola IC.1 ELECTRICAL CHARACTERIZATION OF COPPER PENETRATION EFFECTS IN SILICON DIOXIDE—J. Cluzel, F. Mondon, D. Blachier, CEA/LETI, Grenoble, France, Y. Morand, ST Microelectronics, Crolles, France , L. Martel, and G. Reimbold, CEA/LETI, Grenoble, France also J. Fourier Univ.-Grenoble, France Copper penetration in thermal oxide is investigated using MOS capacitors by annealing and bias-temperature stress. Copper induces minority carrier generation lifetime decay and oxide leakage current increase. SIMS confirms that Cu⁺ ions promote electron injection at the SiO₂-Si interface and electron conduction in the oxide according to a Poole-Frenkel model. IC.2 ELECTROMIGRATION THRESHOLD LENGTH EFFECT IN DUAL DAMASCENE COPPER OXIDE INTERCONNECTS—L. Arnaud, CEA-LETI, Grenoble, France A value of 3000 A/cm is obtained at 250°C for electromigration threshold length product in electroplated dual damascene copper-oxide interconnects. Electromigration lifetimes and failure analysis provide data for temperature ranging from 200°C to 270°C. These data are compared to available threshold products in Cu and AlCu interconnects. IC.3 withdrawn IC.4 RECOVERY OF OPEN VIA AFTER ELECTROMIGRATION IN Cu DUAL DAMASCENE INTERCONNECT—Y. Sun, (on leave from Beijing Polytechnic Univ., Beijing, China) P. Zhou, D.-Y. Kim, K.E. Goodson and S.S. Wong, Stanford Univ., Stanford, CA In this paper, a new failure phenomenon: Open-recovery is investigated in Cu dual Damascene interconnects, An in-situ infrared microscope technique is introduced to monitor the electromigration behavior of electroplated Cu dual Damascene via chains. It is observed that the via that has opened up during electromigration stress test is able to recover completely after storage even at room temperature. The impact of the stress current, storage time and temperature on the recovery has been studied under various conditions. A strong backflow effect is measured in Cu vias after electromigration stressing due to the compressive stress inside interconnects. It is believed that the recovery results from the backflow of Cu ions and a stress model is proposed to explain the recovery mechanism. Tuesday, April 9, 7:00 p.m., Union Station NON VOLATILE MEMORY POSTERS Co-Chairs: Fred G. Kuper, Philips and Neal R. Mielke, Intel NV.1 A COMPLETE STUDY OF SILC EFFECTS ON EEPROM RELIABILITY—L. Larcher, S. Bertulu, and P. Pavan, Università di Modena, Modena, Italy A new compact model including SILC effects accurately predicts Vt shifts in EEPROM cells. This model allows new investigations of the retention dependence on Program/Erase cycles, oxide thickness scaling and quality, and electric field. NV.2 EFFECTS OF FOWLER NORDHEIM TUNNELING STRESS vs CHANNEL HOT ELECTRON STRESS ON DATA RETENTION CHARACTERISTICS OF FLOATING GATE NON-VOLATILE MEMORIES—M. Suhail, T. Harp, J. Bridwell, and P.J. Kuhn, Motorola Semiconductor Products, Austin, TX Data loss is studied in memory cells cycled with CHE programming and source tunnel erase. Bias studies find most of the leakage defects to be over the source, but a significant drain contribution suggests that CHE programming also contributes to the damage. Both source and drain mechanisms deactivate in high-temperature bakes, suggesting a common mechanism. Wednesday, April 10, 8:00 a.m., location Landmark A-B 3A ESD/LATCHUP Co-Chairs: Jeremy C. Smith, TI and Stephen G. Beebe, AMD 3A.2 INVESTIGATION OF GATE TO CONTACT SPACING EFFECT ON ESD ROBUSTNESS OF SALICIDED DEEP SUBMICRON SINGLE FINGER NMOS TRANSISTORS—K.-H. Oh, Stanford Univ., Stanford, CA This paper presents a detailed investigation of the influence of gate to source and gate to drain contact spacings on ESD robustness for a saliciced 0.13 µm technology and gives new insight into the behavior of ESD protection devices. In addition, the present work gives comprehensive modeling and analysis of the device physics involved in this new phenomenon for efficient and robust ESD protection designs.

3A.3 NOVEL ESD PROTECTION STRUCTURE WITH EMBEDDED SCR LDMOS FOR SMART POWER TECHNOLOGY—J.H. Lee, J.R. Shih, R.Y. Shiue, T.C. Ong, Y.K. Peng, and J.T. Yue,TSMC, Hsin-chu, Taiwan ROC

The embedded SCR with P+ straps inserted into N+/NW and N+/P_Sub regions has been successfully developed and implemented into conventional LDMOS device for improving the power transistor ESD performance. The ESCR-LDMOS can increase HBM failure threshold voltage to 8KV and MM failure voltage to 800V without changing any IV characteristics of LDMOS device during normal operation voltage.

3A.4 ESD CIRCUIT SIMULATION FOR THE PREVENTION OF ESD FAILURES — APPLICATION TO PRODUCTS IN A 0.18 µm CMOS TECHNOLOGY—H. Wolf, H. Gieser, Fraunhofer Institut ZM, Munich, Germany, W. Stadler, and K. Esmark, Infineon Technologies, Munich, Germany

This paper describes the ESD circuit simulation of MOS transistors processed in a 0.18 µm CMOS technology. Extending previous work, the model will be explained together with a parameter extraction methodology which also includes device simulation. The model is verified by means of test circuits. The applicability of that approach to the "real world" is proven by revealing failure.

3A.5 ELECTROSTATIC DISCHARGE INDUCED OXIDE BREAKDOWN CHARACTERIZATION IN A 0.1 µm CMOS TECHNOLOGY—A. Salman, George Mason Univ., Fairfax, VA, R. Gauthier, E. Wu, IBM, Essex Jct., VT, P. Riess, InfineonTechnologies, Hopewell Jct., NY, C. Putnam, M. Muhammad, IBM, Essex Jct., VT, M. Woo, OAO Services Inc., Durham, NC, and D. Ioannou, George Mason Univ., Fairfax, VA

As the oxide thickness shrink ESD failures are increasingly due to oxide breakdown rather than source-to-draw filamentation for a 0.1 µm CMOS technology. Using Id-Vg measurements we show how the oxide degrades before failure is detected with the current failure criteria used. The latent effects of oxide degradation on the second breakdown current (IT2) are identified. As the device ages from an oxide perspective, its ESD protection in ultra-thin oxide devices (15A) is shown to reduce.

Wednesday, April 10, 10:30 a.m., location Landmark A-B

3B COMPOUND SEMICONDUCTOR I

Co-Chairs: Wallace T. Anderson, NRL and Anthony Immorlica, BAE Systems

3B.1 HIGH CURRENT TRANSMISSION LINE PULSE (TLP) AND ESD CHARACTERIZATION OF A SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR WITH CARBON INCORPORATED—B. Ronan, Princetown Univ., Princeton, NJ, S.H. Voldman, L.D. Lanzerotti, J. Rascoe, D. Sheridan, and K. Rajendran, IBM, Essex Jct., VT

Electrostatic discharge (ESD) testing of a SiGe heterojunction bipolar transistor (HBT) with the incorporation of Carbon in the base region is discussed for the first time. TLP, human body model (HBM) , and machine model (MM) results of 45 GHz/60 GHz and 120 GHz/100 GHz (f_T/f_MAX) SiGeC HBT devices and ESD power clamp circuits are shown. Results show Carbon improves the TLP voltage-to-failure distribution.

3B.2 WAFER LEVEL FORWARD CURRENT RELIABILITY ANALYSIS OF 120GHZ PRODUCTION SiGe HBTS UNDER ACCELERATED CURRENT STRESS—J.-S. Rieh, IBM, Hopewell Jct., NY, K. Watson, A. Joseph, IBM, Essex Jct., VT, G. Freeman, S. Subbanna, IBM, Hopewell Jct., NY

Forward mode current reliability of 120 GHz f_T self-aligned polysilicon emitter SiGe (HBTs) heterojunction bipolar transistor, which is increasingly important for high speed operations, is described for the first time. Wafer level accelerated stress is employed utilizing collector current density ranging up to as high as Jc=34 mA/µm² .

3B.3 PHYSICAL MECHANISMS OF PERFORMANCE INSTABILITIES SUCH AS GATE-LAG AND KINK PHENOMENA IN GaAs MESFETs—Y. Mitani, A. Wakabayashi, and K. Horio, Shibaura Institute of Technology, Saitama, Japan

Slow current transients during turn-on (gate-lag) and abnormal increases in drain conductance (kink) in GaAs metal semiconductor field effect transistors (MESFETs) are studied by 2D analysis considering surface states. Particularly it is discussed how the gate-lag is influenced by impact ionization of carriers and how the kink depends on structural parameters such as gate length and distance between source and gate.

Wednesday, April 10, 8:00 a.m., location Landmark C-D

3C FAILURE ANALYSIS

Co-Chairs: Travis M. Eiles, Intel and Michael R. Bruce, AMD

3C.1 RECOVERY OF SHIFTED MOS PARAMETERS INDUCED BY FOCUSED ION BEAM EXPOSURE—K. Chen, H. Edwards, T. Chatterjee, J. Parker, and T. Henderson, TI, Dallas, TX

Focused ion beam (FIB) can cause MOS parameter changes when it is used to isolate circuits in failure analysis. The threshold voltage could shift as much as a few 10th volts if a gate of a transistor was cut using FIB. This work demonstrated that parameter changes induced by FIB could be recovered by using an annealing process.

3C.2 withdrawn

3C.3 RELIABILITY OF ULTRA THINNING OF FLIP CHIPS FOR THROUGH-SILICON ANALYSES—E. Le Roy, C.-C. Tsao, Schlumberger Technologies, San Jose, CA, S. Saha, M.E. Potter, Agere Systems, Allentown, PA

This study addresses the needs of ultra-thin silicon substrate of integrated circuit (IC) and demonstrates a technique to reliably thin and polish the silicon substrate of flip-chip packaged ICs globally to a nominal thickness of 10 microns. This technique uses a conventional lapping tool with the aids of a reflectance spectrometer for thickness monitoring. This combination enables to achieve target thickness at high precision (± 1 micron) reliably in a short period time (< 1 hour).

3C.4 NEURAL NETWORK CLASSIFICATION OF PHOTOEMISSION SPECTRA—S.J. Frank, Texas Instruments, Dallas, TX

While the relationship between photoemission spectra and defects in integrated circuits has been well documented, the routine use of photoemission spectroscopy has been hampered by the difficulty of classifying the spectrum in the presence of noise. This paper proposes a neural network as the solution to this problem.

3C.5 PHYSICAL ANALYSIS OF TI-DIFFUSION IN 33 Å GATE OXIDE BREAKDOWN—K.L. Pey, National Univ. of Singapore, Singapore, C.H. Tung, Institute of Microelectronics, Singapore, W.H. Lin, Chartered Semiconductor Mfg., Singapore, M.K. Radhakrishnan, Institute of Microelectronics, Singapore

Abnormal titanium diffusion is found in Ti-silicided 0.18 µm transistor after constant voltage stress that leads to titanium "diffusion" towards 33 Å gate oxide and Si substrate. Ultra-thin layers of titanium were detected at oxide/polySi and oxide/substrate interface even before oxide breakdown, leading to possible transistor early failure by this new mechanism.

Wednesday, April 10, 10:30 a.m., location Landmark C-D

3D PRODUCT RELIABILITY I

Co-Chairs: Robert V. Knoell, Visteon and Walter C. Riordan, Intel

3D.1 SOFT ERROR RATE MITIGATION TECHNIQUES FOR MODERN MICROCIRCUITS—D.G. Mavis, P.H. Eaton, Mission Research Corp., Albuquerque, NM

A unique circuit design technique is described which totally eliminates alpha and neutron induced soft errors from deep submicron microcircuits. The technique, termed "temporally redundant sampling", addresses both static latch upsets and transient induced errors. The approach has minimal impact on the design flow, physical layout area, and circuit performance.

3D.2 SER RELIABILITY OF 1TRAM DESIGNS—D. Sinitsky, S. Peng, J. Wang, T.C. Ong, TSMC, Hsin-Chu, Taiwan, F.C. Hsu, Mosys Inc., Santa Clara, CA, and E. Chen, TSMC, Hsin-Chu, Taiwan

The soft error rates (SER) of 1TRAM memory circuits is investigated using active and refresh modes, different frequencies, temperatures, voltages, manufacturing conditions, and cell capacitance parameters. The 1TRAM design shows good scaling capability as compared to SRAM SER. The weak dependence of 1TRAM SER on critical charge ensures 1TRAM is robust across manufacturing process variations.

Wednesday, April 10, 2:00 p.m., location Landmark A-B

4A COMPOUND SEMICONDUCTOR II

Co-Chairs: Wallace T. Anderson, NRL and
Anthony Immorlica, BAE Systems

4A.1 RELIABILITY TEST OF MESFETs IN PRESENCE OF HOT ELECTRONS—S. Mil'shtein, Univ. of Massachusetts Lowell, Lowell, MA, P. Ersland, M/A-COM, Lowell, MA, and C. Gil, Univ. of Massachusetts Lowell, Lowell, MA

Temperature profiles of hot electrons were modeled in GaAs metal semiconductor field effect transistors (MESFETs) undergoing stress tests, where the gate voltage was close to pinch-off and the drain voltage was slightly lower than breakdown. These profiles were compared with the results of degradation during the stress. We discuss the probability of various defect formation resulting from this stress.

4A.2 INNOVATIVE NITRIDE PASSIVATION ON PSEUDOMORPHIC GaAs HEMTs AND ITS IMPACT ON DEVICE’S PERFORMANCE—Y.-C. Chou, P. Nam, H.K. Kim#, R. Lai, G.P. Li*, Y. Ra#, M. Biedenbender, and A. Oki, TRW, Redondo Beach, CA
#Bathel Material Research, Placentia, CA *UC Irvine, Irvine, CA

Innovative nitride passivation using high-density inductive coupled plasma chemical vapor deposition (HD-ICP-CVD) on pseudomorphic GaAs high electron mobility transistors (HEMTs) was investigated. The evaluation of device performance after passivation shows a strong dependence upon deposition conditions such as plasma power density and system configuration. Evaluation of devices after post stabilization bake shows a performance improvement over conventional PECVD nitride passivation devices. The changes of device performance are attributed to the surface property modification by the high-density plasma process on the recess regions of both source and drain sides on pseudomorphic GaAs HEMTs.

4A.3 EVOLUTION OF DC AND MICROWAVE DEGRADATION INDUCED BY HIGH-TEMPERATURE ACCELERATED LIFETEST OF PSEUDOMORPHIC GaAs AND InGaAs/InAlAs/InP HEMT MMICs—Y.-C. Chou, D. Leung, R. Lai, R. Grundbacher, J.R. Scarpulla, M. Barsky, D. Eng, P.H. Liu, A. Oki, and D. Streit, TRW, Redondo Beach, CA

The evolution of DC and microwave degradation induced by 3-temperature accelerated lifetest of pseudomorphic GaAs and InGaAs/InAlAs/InP HEMTs was investigated. The results show a distinct difference of degradation evolution in these two technologies. The understanding of degradation evolution leads to different approaches to improving the high-temperature reliability performance of pseudomorphic GaAs and InGaAs/InAlAs/InP HEMTs.

Wednesday, April 10, 3:15 p.m., location Landmark A-B

4B DEVICE & PROCESS

Co-Chairs: Prasad Chaparala, National Semiconductor and
Srikanth Krishnan, Texas Instruments

4B.1 IMPACT OF NEGATIVE BIAS TEMPERATURE INSTABILITY ON DIGITAL CIRCUIT RELIABILITY—V.K. Reddy, A.T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T.A. Rost, and S. Krishnan, Texas Instruments, Dallas, TX

Through static Negative Bias Temperature Instability (NBTI) stress of a ring oscillator circuit, we have unambiguously determined the circuit reliability impact of NBTI. The relative frequency degradation of the stressed ring oscillator increases as the operating voltage decreases and is due to increased transistor parametric degradation with decreasing supply voltage and reduced voltage headroom. NBTI stress can also result in SRAM static noise margin degradation.

4B.2 LEAKAGE CURRENT AND RELIABILITY EVALUATION OF RE-OXIDIZED NITRIDE AND CONVENTIONAL OXIDES—E.Y. Wu, IBM, Essex Jct., VT, R.-P. Vollertsen, Infineon Technologies, Essex Jct., VT, R. Jammy, IBM, Hopewell Jct., NY, A. Strong, IBM, Essex Jct., VT, C. Radens, IBM, Hopewell Jct., NY

In this paper, a systematic and detailed investigation of leakage current and TDDB measurements of re-oxidized nitride in comparison with conventional oxides is reported. Leakage current characteristics, thickness dependence of time/charge-to-breakdown (T_BD and Q_BD), both voltage and temperature dependence of T_BD and Q_BD, and thickness dependence of Weibull slopes have been carefully examined. Conventional oxides are shown to be superior as compared to the re-oxidized nitrides in many aspects, indicating that high quality oxides can offer a thickness scaling option for storage applications.

4B.3 EXTENDING THE RELIABILITY SCALING LIMIT OF GATE DIELECTRICS THROUGH REMOTE PLASMA NITRIDATION OF N₂-O-GROWN OXIDES AND NO RTA TREATMENT—C.H. Liu, H.-S. Lin, Y.Y. Lin, M.G. Chen, K.T. Huang, S. Lin, C.T. Huang, T.M. Pan, Y.C. Sheng, W.T. Chang, J.H. Lee, M. Huang, S. Huang-Lu, C.S. Hsiung, W.Y. Hsieh, P.W. Yen, S.C. Chien, Y.T. Loh, Y.J. Chang, and F.-T. Liou, United Microelectronic Corp., Hsin-Chu, Taiwan ROC

A new gate dielectric process (N₂O+RPN+NO) has been developed by remote plasma nitridation of N₂O oxides followed by rapid thermal NO annealing for the use of 0.1 µm technology and possibly beyond. These 14 Å films show excellent interface properties, significantly reduced leakage current, and superior reliability compared to other dielectrics of same thickness.

4B.4 N-FET HCI RELIABILITY IMPROVEMENT BY NITROGEN INTERSTIALIZATION AND ITS MECHANISM—J.R. Shih, M.C. Chiang, H.C. Lin, R.Y. Shiue, Y.K. Peng, and J.T. Yue, TSMC, Hsin-Chu, Taiwan ROC

A new LDD scheme formation with N₁₄ and P₃₁ co-implant through TEOS liner has been proposed to improve NFET's hot carrier lifetime. The 10 × improvement in lifetime is attributed to apparent Isub reduction that is caused by profile modulation of P₃₁ and B₁₁ in the LDD region by TED effect enhanced by N₁₄ implant-induced interstabilization.

4B.5 MECHANISM OF DEVICE DEGRADATION UNDER AC STRESS IN LOW-TEMPERATURE POLYCRYSTALLINE SILICON TFTS—Y. Toyota, T. Shiba, and M. Ohkura, Hitachi Ltd., Tokyo, Japan

Device degradation of poly-si thin film transistors (TFTs) under DC and AC stresses is quantitatively analyzed. The device degradation of a single drain TFT is pronounced, whereas the LDD TFT is less impacted, and is dominated by effective Drain Avalanche Hot Carrier ( DAHC) stress. A new degradation mechanism that considers hot-holes is proposed.

Wednesday, April 10, 2:00 p.m., location Landmark C-D

4C PRODUCT RELIABILITY II

Co-Chairs: Robert V. Knoell, Visteon and Walter C. Riordan, Intel

4C.1 EVALUATION OF STI DEGRADATION CAUSING DRAM STANDBY CURRENT FAILURE IN BURN-IN MODE OPERATION USING A CARRIER INJECTION METHOD—S.-W. Hong, G.-Y. Jin, H.-W. Seo, J.-H. Song, J.-Y. Noh, Y.-C. Oh, J.-Y. Kim, D.-H. Kim, H.-H. Kim, D.-J. Won, W.-W. Lee, D.-H. Song, K.-Y. Lee, and W.-S. Lee, Samsung Electronics, Yongin, Korea

P+ to p+ isolation degradation that causes DRAM standby current failure under burn-in mode operation is investigated. Although the isolation test device does not show any degradation or weakness in conventional electrical characterization, the degradation can be observed by a carrier injection method. Using the simple carrier injection method to simulate the real operating condition of a chip, a potential problem of isolation degradation can be easily found which cannot be screened by conventional electrical measurement.

4C.2 CHARGE TRAPPING INDUCED DRAM DATA RETENTION TIME DEGRADATION UNDER WAFER-LEVEL BURN-IN STRESS—H.W. Seo, G.-Y. Jin, K.-H. Yang, Y.-J. Lee, J.-H. Lee, D.-H. Song, Y.-C. Oh, J.-Y. Noh, S.-W. Hong, D.-H. Kim, J.-Y. Kim, H.-H. Kim, D.-J. Won, and W.-S. Lee, Samsung Electronics, Yongin, Korea

The degradation of DRAM data retention time is investigated using wafer burn-in characteristics. It is experimentally demonstrated that the data retention time degradation is due to the enhanced GIDL from the increased electric field caused by electron trapping in the gate oxide during wafer burn-in stress.

4C.3 A TECHNIQUE TO PREDICT GATE OXIDE RELIABILITY USING FAST ON-LINE Q_BD TESTING—E. Mullen, C. Leveugle, J. Molyneaux, Analog Devices, Limerick, Ireland, J. Prendergast, Institute of Technology, Kerry, Ireland, and J.S. Suehle, NIST, Gaithersburg, MD

QBD testing using 1) fixed initial current, and 2) fixed initial current density are compared and contrasted to package level constant voltage TDDB testing. Oxides area dependencies are also investigated.

Wednesday, April 10, 3:15 p.m., location Landmark C-D

4D INTERCONNECTS

Co-Chairs: Michael J. Dion, Intersil and James A. Walls, Motorola

4D.1 (INVITED)—INVESTIGATION OF VIA-DOMINATED MULTI-MODAL ELECTROMIGRATION FAILURE DISTRIBUTIONS IN DUAL DAMASCENE Cu INTERCONNECTS WITH A DISCUSSION OF THE STATISTICAL IMPLICATIONS—J.P. Gill, T.D. Sullivan, S. Yankee, IBM, Essex Jct, VT, H. Barth, A. von Glasow, Infineon, Munich, Germany

Electromigration results for a 264 sample electromigration study performed on dual damascene copper interconnects are presented and reviewed. The stress results show multi-modal failure distributions, and extensive failure analysis provides possible explanations as to the failure modes. Monte-Carlo type simulations are used to investigate the statistical implications of using bi-modal fitting to predict reliability performance.

4D.2 PSEUDO-BREAKDOWN EVENTS INDUCED BY BIASED-THERMAL-STRESSING OF INTRA-LEVEL Cu INTERCONNECTS – RELIABILITY & PERFORMANCE IMPACT—W.S. Song, T.J. Kim, T.K. Kim, C.S. Lee, J.W. Kim, S.Y. Kim, D.K. Jeong, K.C. Park, Y.J. Wee, B.S. Suh, S.M. Choi, H.-K. Kang, J.T. Moon, and S.U. Kim, Samsung Electronics, Seoul, Korea

Pseudo-breakdown (PBD) phenomenon has been characterized in intra-level reliability assessment of Cu-interconnects. Field and intra-level spacing dependence show that PBDs form an irreversible permanent damage path that differs from HBDs by the amount of Joule energy stored prior to the breakdown event. An RC delay simulation demonstrates that PBD leakage may hinder the circuit performance with further device scale down. Failure analysis reveals the lower liner/IMD interface as the predominant leakage path accompanying PBDs.

4D.3 STRESS-INDUCED VOIDING UNDER VIAS CONNECTED TO WIDE CU METAL LEADS—E. Ogawa, J.W. McPherson, J.A. Rosal, K.J. Dickerson, T.-C. Chiu, L.Y. Tsung, M.K. Jain, T.D. Bonifield, J.C. Ondrusek, and W.R. McKee, Texas Instruments, Dallas, TX



	An exponential decay (ED) transient current in a biased MOS capacitor that flows prior to the 1/t transient current is found. The ED transient current is found to be caused by hole capturing at an Si/SiO₂interface state with an energy level of 0.2 eV from the bottom of the Si conduction band. The origin of the interface state is considered to be a weak Si-O bond at the interface. 6.3 MODELING OF SUBSTRATE RELATED EXTRINSIC OXIDE FAILURE DISTRIBUTIONS—T. Pompl, M. Kerber, M. Obry, A. Krasemann, and D. Temmler, Infineon Technologies, Munich, Germany The extrinsic defect density of 6.8 nm oxide on different H₂ annealed CZ Si wafers was investigated in detail. All measured extrinsic distributions can be explained by one single oxide thickness distribution of oxide thinning in COPs. The result indicates that substrate defects cause an extrinsic fail only at the late stage of chip operation. 6.4 SOFT BREAKDOWN ENHANCED HYSTERESIS EFFECTS IN ULTRA-THIN OXIDE SOI nMOSFETS—M.C. Chen, C.W. Tsai, S.H. Gu, T. Wang, National Chiao-Tung Univ., Hsin-Chu, Taiwan ROC, S.H. Lu, E. Lin, S.C. Chien, Y.T. Loh, and F.T. Liu, United Microelectronic Corp., Hsin-Chu, Taiwan ROC Two soft breakdown enhanced threshold voltage hysteresis modes are identified in ultra-thin oxide (1.6 nm) PD-SOI nMOSFETs. In a MOSFET with breakdown over the channel, excess holes, attributed to valence-band tunneling, flow to the floating body and thus enhance threshold voltage hysteresis in gate bias switching. In a MOSFET with breakdown over the drain, enhanced threshold voltage hysteresis is observed in drain bias switching due to increased band-to-band current. 6.5 TIME-DEPENDENT DIELECTRIC BREAKDOWN IN POLY-SI CVD HfO₂ GATE STACK—S.-J. Lee, C.H. Lee, C.H. Choi, W.P. Bai, Y.H. Kim, and D.L. Kwong, The Univ. of Texas, Austin, TX The area dependence and temperature acceleration (25-150 °C) of TDDB, defect generation rate, and critical defect density of CVD HfO₂ gate stacks with polysilicon is studied. Due to a larger physical thickness and thermal stability, reduced leakage current, comparable Weibull slope and critical defect density with thick SiO₂, the CVD HfO₂ gate stacks show excellent TDDB properties