Tuesday, March 23, 8:15 a.m. — Plenary Session

1.1 Microprocessor Reliabiliity Performance as a Function of Die Location for a 0.25µm Five Layer Metal CMOS Logic Process—W.C. Riordan/R. Miller/J.M. Sherman/J. Hicks, Intel

1.2 Study on Reliability of Ta2O5/Rugged Si Capacity of 23 µC/µm2 Applied to High Density DRAMs Using Sub-0.2µm Process—Y. Ohji/S. Iijima/A. Saito/H. Miki/M. Kanai/M. Kunitomo/S. Yamamoto/ R. Furukawa/Y. Sugawara/T. Uemura/J. Kuroda/M. Nakata/ T. Kisu/T. Kawagoe/K. Kawakita/M. Hasegawa/M. Nakamura/K. Kajigaya/M. Hidaka/H. Yamamoto/I. Asano, Hitachi Ltd.

1.3 A New Physical Model for NVM Data-Retention Time-To-Failure—B. De Salvoa,b/G. Ghibaudoa/G. Pananakakisa,/B. Guillaumoto, /P. Candelierb,o/G. Reimboldb    a LPCS/ENSERG   bST Microelectronics  oCEA/LETI

1.4 Using Erase Self-Detrapped Effect to Eliminate the Flash Cell Program/Erase Cycling Vth Window Close—J-H. Lee/K.R. Peng/J-R. Shih/B.K. Liew/J.Y.C. Sun, Taiwan Semiconductor Manufacturing Company

1.5 Interconnect and MOS Transistor Degradation at High Current Densities—A. Neugroschel/C-T. Sah, University of Florida

1.6 The Influence of Stud Bumping Stress on the Device Degradation in Scaled MOSFETs—N. Shimoyama/K. Machida/M. Shimaya/H. Koizumi/H. Kyuragi, NTT System Electronic Laboratories

1.7 Off-State Stress-Induced Reduction of Off-State Current in Polycrystalline Silicon Thin Film Transistors—A.T. Krishnan/S.J. Fonash, Pennsylvania State University

Tuesday March 23, 2:00 p.m.— Parallel Session

2A.1 A Unified Gate Oxide Breakdown Reliability Model—C. Hu/Q. Lu, UC Berkeley

2A.2 Field Dependent Critical Trap Density for Thin Gate Oxide Breakdown—K.P. Cheung/C.T. Liu/C-P. Chang/J.I. Colonell/W.Y-C Lai/R. Liu/J.F. Miner/C.S. Pai/H. Vaidya/J.T. Clemens, Lucent Bell Labs/E. Hasegawa, NEC Corp.

2A.3 Challenges for Accurate Projections in the Ultra-Thin Oxide Regime—E. Wu/W. Abadeer/L.K. Han/G. Hueckel/S.H. Lo, IBM

2A.4 Study of Oxide Breakdown Under Very Low Electric Field—A. Teramoto/H. Umeda/K. Azamawari*/K. Kobayashi/K. Shiga/J. Komori/Y. Ohno/H. Miyoshi, Mitsubishi Electric Corporation         *TADA Electric Corp.

2A.5 The Statistical Dependence of Oxide Failure Rates on the Vdd and tox Variation, with Applications for Process Design, Circuit Design, and End Use—W. R. Hunter, Texas Instruments

2A.6 Influence of Soft Breakdown on NMOSFET Device Characteristics—T. Pompl, Siemens/H. Wurzer, SIMEC/R.C. Wilkins, University of Newcastle/M. Kerber, Siemens

2A.7 Charge Trapping Mechanism under Dynamic Stress and its Effect on Failure Time—G.Ghidini/D. Brazzelli/C.Clementi/F. Pellizzer, ST Microelectronics

2A.8 Re-challenge of Fluorine Incorporation into SiO2 - Significant Improvement of Charge-to-Breakdown Distribution—Y. Mitani/H. Satake/Y. Nakasaki/A.Toriumi, Toshiba Corporation

Tuesday March 23, 2:00 p.m.— Parallel Session

2B.1 Reliability of Passivated 0.15µm InAlAs/InGaAs HEMTs with Pseudomorphic Channel—M. Dammann/M. Chertouk/W. Jantz/K. Köhler/K.H. Schmidt/G. Weimann, Fraunhofer Institut fur Angewandte Festkörperphysik

2B.2 Reliability Evaluation of MOCVD Grown AlInAs/GaInAs/InP HEMTs—M. Nawaz, Chalmers Univ. of Technology/W. Strupinski, Institute of Electronic Materials Technology/J. Stenarson/S.H.M Persson/H. Zirath, Chalmers University of Technology

2B.3 Bulk and Surface Effects of Hydrogen Treatment on Al/Ti Gate AlGaAs/GaAs Power HFETs—R. Gaddi, Univ. of Modena/R. Menozzi, Univ. of Parma/A. Castaldini, Univ. of Bologna/C. Lanzieri, Un'Azienda Finmeccanica S.p.A./G. Meneghesso, Univ. of Padova/C. Canali, Univ. of Modena/E. Zanoi, Univ. of Padova

2B.4 Threshold Voltage Shift in 0.1µm Self-Aligned Gate GaAs MESFETs Under Bias Stress and Related Degradation of Ultra-High Speed Digital ICs—Y.K. Fukai/K. Yamasaki/K. Nishimura, NTT System Electronics Laboratories

2B.5 Full Two-dimensional Electroluminescent (EL) Analysis of GaAs/AlGaAs HBTs—M. Harris/B.Wagner/S. Halpern/M. Dobbs, Georgia Tech Research Institute/C.Pagel/ B. Stuffle/J. Henderson/K. Johnson, Naval Surface Warfare Center

2B.6 A TDDB Model of Si3N4 based Capacitors in GaAs MMICs—J. Scarpulla/D.C. Eng/S.R. Olson/C-S. Wu, TRW

Wednesday March 24, 8:15 a.m.—Parallel Session

3A.1 Occurrence and Elimination of Anomalous Temperature Dependence of Latchup Trigger Currents in BICMOS Processes—E.R. Ooms, /J.A. van der Pol, Philips Semiconductors

3A.2 High-Current Pulsed Characterization of Dual-Damascene Copper Interconnects in Low and High-K Interlevel Dielectrics in Advanced CMOS Semiconductor Technologies—S. Voldman/R. Gautheir/K. Morrisseau/M. Hargrove/V. McGahay, IBM

3A.3 The Effect of Silicide on ESD Performance—G. Notermans/A. Heringa/M. van Dort/S. Jansen/F. Kuper, Philips Semiconductor

3A.4 Analysis of Snapback Behavior on the ESD Capability of Sub-0.20µm NMOS—A. Amerasekera/V. Gupta/K. Vasanth, Texas Instruments,  Inc.

3A.5 Modular Approach of a High Current MOS Compact Model for ESD Circuit-Level Simulation Including Transient Gate Coupling Behavior—M. Mergens/W. Wilkening, Robert Bosch GmbH/H. Wolf, Fraunhofer Festkörpertechnologie FT/S/W. Fichtner, Swiss Federal Institute of Technology

Wednesday March 24, 8:15—Parallel Session

3B.1 Performance and Reliability of a New MEMS Electrostatic Lateral Output Motor—S.T. Patton/W.D. Cowan/J.S. Zabinski, Air Force Research Laboratory

3B.2 The Effect of Humidity on the Reliability of a Surface Micro-machined Microengine—D.M. Tanner/K.A. Peterson/L.W. Irwin/N.F. Smith/W.P. Eaton/W.M. Miller/S.L. Miller, Sandia National Laboratories

3B.3 Laser Power Monitoring Using MOEMS Micromirror Technology—A. Agarwal/S. Arney/B. Barber/S. Kosinski/J. LeGrange/R. Raju/R. Ruel, Lucent  Bell Labs

3B.4 Reliability Methodology for Prediction of Micromachined Accelerometer Stiction—A. Hartzell/D. Woodilla, Analog Devices Inc.


3C.1 The Relationship Between Resistance Changes and Void Volume Changes in Passivated Al Interconnects—J. Doan/J. Bravman/P. Flinn, Stanford University/T.Marieb, Intel Corporation

3C.2 A Novel Fast Technique for Detecting Voiding Damage in IC Interconnects—S. Foley/L. Floyd/A. Matthewson, University College  Cork Ireland

3C.3 Significant Improvement in Electromigration of Reflow-Sputtered Al-0.5wt% Cu/Nb-Liner Dual Damascene Interconnects with Low-k Organic SOG Dielectric—T. Usui/T.Watanabe/S. Ito/M. Hasunuma/M. Kawai/H. Kaneko, Toshiba Corporation

3C.4 The Apparent Activation Energy and Current Density Exponent of Electromigration Damage in Chip Level Interconnect Lines: A Grain-Structure-Based Statistical Approach—M.A. Korhonen/T.M. Korhonen, Cornell University/D.D. Brown, Advanced Micro Devices, Inc./C.-Y. Li, Cornell University

Wednesday March 24, 2:00 p.m.—Parallel Session

4A.1 ESREF Best Paper (Invited) Precise Quantitative Evaluation of the Hot Carrier Induced Drain Series Resistance Degradation in LATID-n-MOSFETs —G.H. Walter/W.Weber/R. Brederlow/R. Jurk/C.G. Linnenbank/C. Schlunder/D.Schmitt-Landsiedel#, /R. Thewes; Siemens AG      #Technical University of Munich

4A.2 Channel Length Dependence of Hot Carrier Degradation of LATID-n-MOSFETs under Analog Operation—R. Thewes/G.H. Walter/R.Brederlow/C.Schlunder/A.V. Schwerin/R. Jurk /C.G. Linnenbank/G. Lengauer/D. Schmitt-Landsiedel#/W.Weber; Siemens AG      # Technical University of Munich

4A.3 Hot Carrier Degradation of the Low Frequency Noise of MOS Transistors under Analog Operating Conditions—R. Brederlow,/W. Weber/D. Schmitt-Landsiedel# /R. Thewes; Siemens AG       #Technical University of Munich

4A.4 A Unified Compact Scalable "delta" Id Model for Hot-Carrier Reliability Simulation—P. Chen/L. Wu/G. Zhang/Z. Liu, BTA Technology, Inc.

4A.5 An Accurate Hot-Carrier Reliability Monitor for Deep-submicron Shallow S/D Junction Thin Gate Oxide n-MOSFETs—S.S. Chung/S.J. Chen/C.M. Yih/W.J. Yang, National Chiao Tung University/T.S. Chao, National Nano Device Laboratory

4A.6 Hot Carrier Effects in nMOSFETs in 0.1µm CMOS Technology—E. Li/E. Rosenbaum, University of Illinois at Urbana-Champaign/J.Tao, AMD/G. Yeap, Motorola/M.-R. Lin/P. Fang, AMD

4A.7 Degradation of Hot Carrier Lifetime for Narrow Width MOSFET with Shallow Trench Isolation—W. Lee, Kwangju Institute of Science and Technology/S. Lee/T. Ahn, LG Semicon Co./H. Hwang, Kwangju Institute of Science and Technology

Wednesday March 24, 2:00 p.m.—Parallel Session

4B.1 Microstructure and Electromigration in Copper Damascene Lines—L. Arnaud/G. Tartavel, LETI CEA-G/T. Berger, SGS Thomson Microelectronics/D. Mariolle/Y.Gobil, LETI CEA-G

4B.2 Surface Electromigration in Copper Interconnects—N.D. McCusker/H.S. Gamble, The Queen's University of Belfast

4B.3 The Leakage Current Degradation of Cu/BCB Single Damascene under Thermal and Bias-Temperature Stress—S.U. Kim, SEMATECH/T. Cho/P.S. Ho, University of Texas

4B.4 Thermal Stresses in L- and T-Shaped Metal Interconnects: A Three Dimensional Analysis—Y.-L. Shen, University of New Mexico

4B.5 The Use of a WLR Technique to Characterize Stress-Induced Voiding in 0.25 and 0.18 Micron Technologies for Integrated Circuits—A. Marathe/P. Besser/J. Tsiang/V. Pham/P. Fang, Advanced Micro Devices, Inc.

4B.6 Investigation of Self-Heating Phenomenon in Small Geometry Vias Using Scanning Joule Expansion Microscopy—K. Banerjee/G. Wu/M. Igeta,UC Berkeley/A. Amersekera, Texas Instruments, Inc./A. Majumdar/C. Hu, UC Berkeley

4B.7 Thermo-Mechanical Stress-Induced Voiding In a Tungsten-AlCu Interconnect System—B. Wallace/Y.-H. Lee/D. Pantuso/K. Wu/N. Mielke, Intel

Thursday, March 25, 8:15 a.m.—Parallel Session

5A.1 Two-dimensional Carrier Profiling of 0.4µm Devices Using Scanning Schottky Capacitance Microscopy—J. Thomson/J.N. Nxumalo/Y. Li/T. Tran, University of Manitoba

5A.2 Threshold Voltage Shift Caused by Copper Contamination—B. Vermeire/C.A. Pederson/H.G. Parks/D. Sarid, University of Arizona

5A.3 Fault Model for VLSI Circuits Reliability Assessment—B. Lisenker/Y. Mitnick, Intel Israel

5A.4 Laser Micro-machining of Silicon and Deposition of Conductor Lines for Design Debug of C4 Packaged ICs—R.R. Goruganthu/M. Bruce/J. Birdsley/V. Bruce/G. Gilfeather, Advanced Micro Devices

5A.5 Failures Induced on Bipolar Operational Amplifiers from Electromagnetic Interferences Conducted on the Power Supplay Rails—N. Specialo/G. Setti, Univ. of Bologna


5B.1 Backside Probing of Flip-Chip Circuits Using Electrostatic Force Sampling—R.Qia/D.J. Thomsona,b/G.E. Bridgesa,b    a Micron Force Instruments Inc.      bUniversity of Manitoba

5B.2 Filler Induced Metal Crush Failure Mechanism in Plastic Encapsulated Devices—P. Yalamanchili/V. Baltazar, Analog Devices Inc.

5B.3 Design Optimization of RF Antenna BGA Interconnect Structures Using Test Validated Physics of Failure Method—D.A. Pietila/M. Rassaian, Boeing Information, Space & Defense Systems

Thursday, March 25, 8:15—Parallel Session

5C.1 U-V Blocking Technology to Reduce Plasma Induced Transistor Damage in Ferroelectric Devices with Low Hydrogen Resistance—S. Shuto/I. Kunishima/S. Tanaka, Toshiba Corporation

5C.2 New Experimental Findings on Process-Induced Hot Carrier Degradation of Deep-Submicron n-MOSFETs—D.Y.C. Lie/J. Yota/W. Xia/A.B. Joshi/R.A. Williams/R. Zwingman/L. Chung, Rockwell Semiconductor Systems/D.L. Kwong, Univ. of Texas at Austin

5C.3 A Model for Channel Hot Carrier Reliability Degradation due to Plasma Damage in MOS Devices—S. Rangan, Pennsylvania State Univ./S. Krishnan/A. Amerasekara/S. Aur, Texas Instruments, Inc./S. Ashok, Pennsylvania State Univ.

5C.4 A New Experimental Approach to Evaluate Plasma Damage in nMOS and pMOS Devices—L. Pantisano/A. Paccagnella/M. Barbazza/A. Scarpa, Univ. of Padova/M.G. Valentini, ST Microelectronics

Thursday, March 25, 2:00 p.m.—Plenary Session

6.1 A fast and simple methodology to predict dielectric breakdown—T. Nigam/R. Degraeve/G. Groeseneken/M. Heyns/H. Maes, IMEC

6.2 Trap-Assisted Tunneling Current Through Ultra-thin Oxide—J. Wu/L.F. Register/E. Rosenbaum, Univ. of Illinois at Urbana-Champaign

6.3 A Model of the Stress Time Dependence of SILC—Q. Lu, UC Berkeley/K.P. Cheung/N.A. Ciampa/C.T. Liu/C-P. Chang/J.I. Colonell/W-Y-C. Lai/R. Liu/J.F. Miner/H. Vaidya/C-S. Pai/J.T. Clemens, Lucent Bell Labs
6.4 Low Voltage Stress-Induced-Leakage-Current in Ultrathin Gate Oxides—P.E.Nicollian/M. Rodder/D.T. Grider/P. Chen/R.M. Wallace/S.V. Hattangady, Texas Instruments, Inc.

6.5 A Comparative Study of SILC Transient Characteristics and Mechanisms in FN Stressed and Hot Hole Stressed Tunnel Oxides—N-K. Zous/T. Wang/C.C. Yeh/C.W. Tsai, National Chiao-Tung University/C. Huang, Macronix Co.

6.6 Withdrawn

6.7 J-Ramp on sub-3nm Dielectrics: Noise as a Breakdown Criteria—G.B. Alers/B.E. Weir/M.R. Frei/D. Monroe, Bell Laboratories, Lucent Technologies