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Tuesday, 19 September 2000 Room A

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09:00	Opening, until 09:15
09:15	ESSCIRC'1999 Best Paper Award, until 09:20
09:20	Future is in Wireless (Invited Paper)
	Y. Neuvo
	Nokia Mobile Phones, Finland
10:10	Coffee Break, until 10:40

Session 1.1:

Analogue Integrated Circuits

	Chairman: Willy Sansen
	Katholieke Universiteit Leuven, Heverlee, Belgium
10:40	Ultra-low Voltage CMOS Cascode Amplifier
	Torsten Lehmann, Marco Cassia
	Technical University of Denmark, Kgs. Lyngby, Denmark
11:05	Curvature Compensated BiCMOS Bandgap with 1 V Supply Voltage
	Piero Malcovati^1, Franco Maloberti^1, Marcello Pruzzi^1, Carlo Fiocchi^2
	^1University of Pavia, Italy
	^2Mikron AG
11:30	Front-end Processor Core for up to 64X Speed CD-ROM Drive in 0.35um CMOS
	Atsushi Wada, Takeshi Otsuka, Kuniyuki Tani, Tetsuro Sawai
	Sanyo Electric Co., Ltd, Anpachi-Gun, Gifu, Japan
11:55	A Dynamically Controllable DC/DC Level Converter and Its Application to High-Speed, Low-Power Circuits
	Tadayoshi Enomoto^1, Hiroaki Shikano^1, Haruya Iwata^1, Masahiro Fujii^2, Nobuhide Yoshida^2
	^1Chuo University, Tokyo, Japan
	^2NEC Corporation
12:20	Lunch Break, until 14:00
14:00	Bluetooth (TM): From Antenna to Silicon (Invited Paper)
	J. Haartsen
	Ericsson Radio Systems, The Netherlands

Session 1.2:

Low Voltage Analogue Filters

	Chairman: Bram Nauta
	University of Twente, Enschede, The Netherlands
14:50	A Micropower Class AB CMOS Kog-domain Filter for DECT Applications
	Dominique Python^1, Christian Enz^2
	^1EPFL - Swiss Federale Institut of Technology, San Jose, United States
	^2CSEM - Centre Suisse d'Electronique et de Microtec
15:15	Low-Voltage Analog Filters using Floating-gate MOSFETs
	Esther O. Rodriguez-Villegas, Adoracion Rueda, Alberto Yufera
	Instituto de Microelectronica de Sevilla, Spain
15:40	Coffee Break, until 16:10

Session 1.3:

Sigma Delta Convertors

	Chairman: Bill Redman-White
	Philips Semiconductors, Southampton, United Kingdom
16:10	A 400MHz 5th-Order CMOS Continuous-Time Switched-Current Sigma-Delta Modulator
	Louis Luh, John Choma, Jeffrey Draper
	University of Southern California, Los Angeles, United States
16:35	A 1.8V MOSFET-Only Sigma-Delta Modulator Using Compensated MOS-Capacitors in Depletion with Substrate Biasing
	Thomas Tille^1, Jens Sauerbrey^2, Manfred Mauthe^2, Werner Kraus^1, Doris Schmitt-Landsiedel^1
	^1Technical University of Munich, Germany, Germany
	^2Infineon Technologies AG, Munich, Germany
17:00	A 73dB SFDR 10.7MHz 3.3V CMOS Bandpass Sigma-Delta Modulator sampled at 37.05MHz
	Paolo Cusinato^1, Fabrizio Stefani^1, Andrea Baschirotto^2
	^1STMicroelectronics, Cornaredo (MI), Italy
	^2University of Lecce
18:00	Reception, until 20:00

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Tuesday, 19 September.2000 Room B

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Session 1.4:

RF Transceivers

	Chairman: Rudolf Koch
	Infineon Technologies, Munich, Germany
10:40	A Low-Power 1GHz Super-Regenerative Transceiver with time-shared PLL control
	Patrick Favre, Norbert Joehl, Phillipe Deval, Michel Declercq, Catherine Dehollain
	EPFL, Lausanne, Switzerland
11:05	A CMOS 2V Quadrature Direct Up-Converter Chip for DCS-1800 Integration
	Marc Borremans^1, Michiel Steyaert^2
	^1K.U.Leuven, ESAT-MICAS, Heverlee, Belgium
	^2K.U.Leuven, ESAT-MICAS
11:30	A 900MHz/1.9GHz Integrated Transceiver and Synthesizer IC for GSM
	Rahul Magoon^1, Joo Leong (Julian) Tham^2, Al Molnar^1, Bernard Pregardier^2, Mihai Margarit^2, Matteo Conta^1, Jackie Cheng^1, Akbar Ali^1, Stephen Lloyd^1
	^1Conexant Systems, Newport Beach, CA, United States
	^2Formerly with Conexant Systems
11:55	A 2-GHz Low-Power Single-Chip CMOS Receiver for WCDMA Applications
	Dennis Yee, Chinh Doan, David Sobel, Brian Limketkai, Sayf Alalusi, Robert Brodersen
	University of California, Berkeley, United States
12:20	Lunch Break, until 14:00

Session 1.5:

RF CMOS Power Amplifiers

	Chairman: Werner Simbürger
	Infineon Technologies AG, Munich, Germany
14:50	A Low Stress 20dBm Power Amplifier for LINC Transmission with 50% Peak PAE in 0.25um CMOS
	Maurice Tarsia, John Khoury, Vito Boccuzzi
	Lucent Bell-Labs, Murray Hill, NJ., United States
15:15	A 700MHz, 1W fully differential Class E power amplifier in CMOS
	Koen Mertens^1, Michiel Steyaert^1, Bart Nauwelaers^2
	^1K.U.Leuven, ESAT-MICAS, Heverlee, Belgium
	^2K.U.Leuven, ESAT-TELEMIC
15:40	Coffee Break, until 16:10

Session 1.6:

RF Low Noise Amplifiers

	Chairman: Qiuting Huang
	ETH Zentrum, ETZ, Zürich, Switzerland
16:10	A Universal Dual Band LNA Implementation in SiGe-Technology for Wireless Applications
	Stephane Catala,, Axel Schmidt
	Infineon Technologies AG, Muenchen, Germany
16:35	A 9mW, 900-MHz CMOS LNA with 1.05dB-Noise-Figure
	Giuseppe Gramegna, Antonio Magazzu', Ciro Sclafani, Mario Paparo, Pietro Erratico
	STMicroelectronics, Catania, Italy
17:00	Using Capactive Cross-Coupling Technique in RF Low Noise Amplifiers and Down-Conversion Mixer design
	Wei Zhuo^1, Sherif Embabi^1, José Pineda^2, Edgar Sánchez-Sinencio^1
	^1Texas A&M University, Allentown, PA, United States
	^2Philips Research Laboratories

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Tuesday, 19 September 2000 Room C

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Session 1.7:

Digital Systems and Signalling

	Chairman: Stefan Rusu
	Intel Corporation, Santa Clara, CA, United States
10:40	A low power reconfigurable 12-tap FIR interpolation filter with fixed coefficient sets
	C. Henning, R. Schwann, V. Gierenz, T. G. Noll
	EECS, Univ. of Technology RWTH Aachen, Germany, Germany
11:05	Optimum voltage swing on on-chip and off-chip interconnects
	Christer Svensson
	Linköping University, Sweden
11:30	Itanium(tm) Processor System Bus Design
	Alper Ilkbahar, Srinivas Venkataraman, Harry Muljono
	Intel Corp., Santa Clara, United States
11:55	Self Calibrating and Adjustable CMOS Pad Driver for Improved Electromagnetic Compatibility
	Ralf Klein^1, Dirk Roemer^1, Herbert Eichfeld^1, Hans-Joerg Pfleiderer^2
	^1Infineon Technologies AG, Munich, Germany, Germany
	^2University of Ulm, Germany
12:20	Lunch Break, until 14:00

Session 1.8:

Systems on Chip

	Chairman: Christer Svensson
	Linköping University, Sweden
14:50	A New Contactless Smartcard IC using an On-Chip Antenna and an Asynchronous Micro-controller
	André Abrial^1, J. Bouvier^1, P. Senn^1, M Renaudin^2, P. Vivet^3
	^1France Telecom R&D, Meylan Cedex, France
	^2TIMA
	^3STMicroelectronics
15:15	Fully Integrated Motor Driver Controller for Hard Disk Drive Using Digital Approach
	Roberto Bardelli^1, Luca Fontanella^1, Federico Forte^1, Giovanni Frattini^1, Giovanni Martinelli^1, Giulio Ricotti^1, Marco Rossi^2
	^1STMicroelectronics S.r.l., Cornaredo (MI), Italy
	^2STMicroelectronics
15:40	Coffee Break, until 16:10

Session 1.9:

Logic Circuits

	Chairman: Albrecht Rothermel
	Universität Ulm, Germany
16:10	High-Speed and Low-Swing On-Chip Bus Interface Using Threshold Voltage Swing Driver and Dual Sense Amplifier Receiver
	Byung-Do Yang, Lee-Sup Kim
	KAIST, Taejon, Korea (South)
16:35	Iterative Self-Timed Multiplier with Early Completion
	Do-Wan Kim, Deog-Kyoon Jeong
	SoEE, Seoul National University, Korea (South)
17:00	Low power self-timed floating-point divider in 0.25um technology
	Jae-Hee Won, Kiyoung Choi
	Seoul National University, Korea (South)

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Wednesday, 20 September 2000 Room A

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08:30	Software-Radio Base-Stations, A Challenge for Analogue IC-Design (Invited Paper)
	A. Rydin
	Ericsson Radio Systems, Sweden

Session 2.1:

Audio Circuits

	Chairman: Juha Kostamovaara
	University of Oulu, Finland
09:20	Battery Supplied Low Power Analog-Digital Front-End for Audio Applications
	Ronald Klootsema^1, Olivier Nys^1, Eric Vandel^1, Daniel Aebischer^1, Pascal Vaucher^1, Olivier Hautier^1, Pierre Bratschi^1, Francois Bauduin^1, Gerard van Oerle^2, Andreas Jakob^2, Stefan Menzl^2
	^1XEMICS SA, Neuchatel, Switzerland, Switzerland
	^2Phonak AG, Stafa, Switzerland
10:10	A 147 dB Dynamic Range Electronic Attenuator for Audiometric Applications with On-Chip 1 W Power Amplifier
	Simona Brigati^1, Fabrizio Francesconi^1, Daniela Fumagalli^2, Guido Grassi^2, Piero Malcovati^3, Matteo Poletti^1
	^1Micronova Sistemi S.r.l., Trivolzio (PV), Italy
	^2Amplifon S.p.A.
	^3University of Pavia
10:10	Coffee Break, until 10:40
10:40	Analogue Design in Deep Submicron CMOS Technology (Invited Paper)
	K. Bult
	Broadcom Netherlands B.V., The Netherlands

Session 2.2:

Continuous Time Filters

	Chairman: A. Rodriguez-Vazquez
	University of Seville, Sevilla, Spain
11:30	An Eighth-Order CMOS Lowpass Filter with 30-120 MHz Tuning Range and Programmable Boost
	Giacomino Bollati^1, Stefano Marchese^1, Rinaldo Castello^2, Marco Demicheli^1
	^1STMicroelectronics, Cornaredo (MI), Italy
	^2Universita' di Pavia
11:55	Programmable direct digital tuning circuit for a continuous-time filter
	Teemu Salo
	Helsinki University of Technology, Espoo, Finland, HUT, Espoo, Finland
12:20	Lunch Break, until 14:00
14:00	SOI CMOS Circuit Design Exposed - Another Dirty Tricks Campaign? (Invited Paper)
	W. Redman-White
	Philips Semiconductors, United Kingdom

Session 2.3:

Programmable Analogue Filters

		Chairman: Erik Bruun
		Technical University of Denmark, Lyngby, Denmark
	14:50	A 350 MHz Programmable Analog FIR Filter Using Mixed-Signal Multiplier
		Huawen Jin, Edward Lee
		Iowa State University, Austin, Texas, United States
	15:15	A 2.7V CMOS Dual-Mode Baseband Filter for PDC and WCDMA
		Tuomas Hollman^1, Saska Lindfors^2, Mika Länsirinne^2, Jarkko Jussila^2, Kari Halonen^2
		^1Electronic Circuit Design Laboratory, HUT, Espoo, Finland
		^2ECDL, HUT
	15:40	Coffee Break, until 16:00
Poster Session, 16:00 - 19:30
		Split-Drain MOST Based Circuit for Measuring Electric Power
		Carlos Alberto dos Reis Filho
		Faculty of Electrical Engineering, UNICAMP, Campinas, SP, Brazil
		Low Power Column ADC for CMOS Imagers
		André van der Avoird, Maarten Vertregt
		Research Scientist, Eindhoven (NL), Netherlands
		Ultra Low Power A/D Converters Using an Enhanced Differential Charge Transfer Amplifier
		illiam Marble, Donald Comer
		American Microsystems, Inc., American Fork, United States
		SiGe Track-and-Hold with HD3=-87dBFS for fck=110MHz, fin=(110MHz-1kHz) and Vin=1Vpp,diff
		Victor Dias^1, Umberto Gatti^2, Franco Maloberti^3
		^1Infineon Technologies AG
		^2Siemens ICN S.p.A. - CLDC C01, Milano, Italy
		^3University of Pavia
		A 2.5Volt 6 bit 600Ms/s Flash ADC in 0.25um CMOS
		Peter Scholtens
		Philips Research Laboratories Eindhoven, Netherlands
		An 8-bit, 1-Gsample/s Folding-Interpolating Analog-to-Digital Converter
		Wein An, C. Andre T. Salama
		University of Toronto, Toronto, Ontario, Canada
		A 2.7V IF-Sampling Delta-Sigma Modulator with +37dBV IIP3 for Digital Cellular Phones
		Saska, Juhani Lindfors^1, Mika Länsirinne^2, Kari Halonen^2
		^1Electronic Circuit Design Laboratory, KTH, Kista, Sweden
		^2Helsinki University of Technology
		Adaptive Noise Shaping ADC Based on LMS Algorithm
		J. Koh^1, G. Han^2, S.H.K. Embabi^2, F. Maloberti^2
		^1Texas A&M University CS
		^2Texas A&M University CS., United States
		A digitally programmable burst-mode 155 Mb/s transmitter for PON
		Marina Doci^1, Carlo Fiocchi^1, Umberto Gatti^2, Umberto Gatti^2, Alberto Profumo^1, Gilbert Promitzer^3
		^1Italtel S.p.A.
		^2Siemens ICN S.p.A. - CLDC C01, Milano, Italy
		^3AMS, Austria
		A 0.8 µm SOI CMOS On-Board Data Handling Bus Modem for Satellite Applications
		Raffaele Boi^1, Simona Brigati^2, Fabrizio Francesconi^2, Carla Ghidini^3, Piero Malcovati^1, Franco Maloberti^1, Matteo Poletti^4
		^1University of Pavia, Italy
		^2Micronova Sistemi S.r.l.
		^3LABEN S.p.A.
		^4Micronova Sistemi S.r.l.
		A 12GHz /128 frequency divider in 0.25um CMOS
		Bram De Muer, Michiel Steyaert
		K.U.Leuven, ESAT-MICAS, Heverlee, Belgium
		An 18-mW 2.5-GHz BiCMOS Dual Frequency Synthesizer with < 10-Hz RF Carrier Resolution
		Woogeun Rhee^1, Biagio Bisanti^2, Akbar Ali^1
		^1Conexant Systems, Inc., Newport Beach, United States
		^2Texas Instruments
		A 500MHz Supply Noise Insensitive CMOS PLL with a Voltage Regulator using DC-DC Capacitive Converter
		Chang-Hyeon Lee^1, Kelly McClellan^2, John Choma^3
		^1Conexant system & USC, 92606, United States
		^2Entrida
		^3USC
		A Novel Structure for DCO PLLs with Equivalent 16 Bit Digital Phase Quantization, Digital Loop Filter and 18ps Long-term Jitter
		Christoph Sandner, Nicola Da Dalt
		Infineon Technologies MDCA, Villach, Austria
		A Channel Selection Filter for a WCDMA Direct Conversion Receiver
		Jarkko Jussila, Aarno Pärssinen, Kari Halonen
		Helsinki University of Technology/ECDL, HUT, Finland
		CMOS Switched-Capacitor Decimation Filter for Mixed-Signal Video Applications
		Fernando Antônio Pinto Barúqui^1, Antonio Petraglia^1, José Epifânio Franca^2, Sanjit Kumar Mitra^3
		^1Federal University of Rio de Janeiro, Rio de Janeiro, RJ, Brazil
		^2Instituto Superior Técnico
		^3University of California
		A CMOS gm-C Polyphase Filter with High Image Band Rejection
		Pietro Andreani^1, Sven Mattisson^1, Bert Essink^2
		^1Dept. of Applied Electronics, Lund University, , Sweden
		^2Ericsson Business Mobile Networks, Enschede
		A CMOS Switched-Capacitor Bandpass Filter with 100 MSample/s Input Sampling and Frequency Downconversion
		Rui Ferreira Neves, José Epifânio da Franca
		Instituto Superior Técnico, Lisbon, Portugal
		A Hilbert sampler/filter and complex bandpass SC filter for I/Q demodulation
		Sami Karvonen, Juha Kostamovaara
		University of Oulu,Electronics Laboratory, Finland
		A low-distortion digitally programmable continuous-time filter and variable-gain amplifier
		Santiago Celma, Justo Sabadell
		Grupo de Diseño Electronico, Zaragoza, Spain
		An Analog CMOS High-Speed Continuous-Time FIR Filter
		Efram Burlingame, Richard Spencer
		Solid-State Circuits Research Laboratory, UC Davis, United States
		APD Implementation to GHz Range Receiver Channel for a Pulsed Time-of-Flight Laser Radar
		Riku Pennala, Ari Kilpelä, Juha Kostamovaara
		University of oulu, Finland
		A low-power microphone preamplifier with EMI canceling
		George Reitsma, Michiel Kouwenhoven, Arnoud Mosterd
		Delft University of Technology, Netherlands
		A 2.8V 200MHz replicating current comparator for convolutional decoders
		Andreas Demosthenous, John Taylor
		University College London, United Kingdom
		New Regulated Voltage Down Converter based on Modified Band-Gap Cells
		Kussener Edith^1, Barthelemy Hervé^2, Kaiser Andréas^3, Roberts Andrew^4, Malherbe Alexandre^4
		^1ISEM-ST Microelectronics
		^2ISEM, Toulon, France
		^3IEMN-ISEN
		^4ST Microelectronics
		A 2GHz Low-Distortion Low-Noise Two-Stage LNA employing low-impedance bias terminations and optimum inter-stage match for linearity
		Peter Shah, Peter Gazzerro, Vladimir Aparin, Ravi Sridhara, Chiewcharn Narathong
		Qualcomm, San Diego, United States
		A high Dynamic Range 3.4 GHz CMOS micropower mixer
		Peter Vancorenland, Philippe Coppejans, Wouter De Cock, Michiel Steyaert
		ESAT-MICAS KULeuven, Heverlee, Belgium
		Generating All 2-Transistor Circuits Leads to New Wide-Band CMOS LNAs
		F. Bruccoleri, E.A.M Klumperdinck, B. Nauta
		MESA+ Research Institute, Enschede, Netherlands
		A Self-Calibrating 900-MHz CMOS Image-Reject Receiver
		Raymond Montemayor, Behzad Razavi
		University of California, Los Angeles, United States
		A New Small Signal Modeling of RF MOSFETs including Charge Conservation Capacitances
		Ickjin Kwon, Minkyu Je, Kwyro Lee, Hyungcheol Shin
		Department of EECS, KAIST, Taejon, Korea (South)
		Influence of substrate noise on RF performance
		Domine Leenaerts, Peter de Vreede
		Philips Research Laboratories, Eindhoven, Netherlands
		A 2.7 V, 8 GHz Monolithic I/Q RC Oscillator with Active Inductive Loads
		Johan van der Tang^1, Dieter Kasperkovitz^2, Francesco Centurelli^3, Arthur van Roermund^1
		^1Eindhoven, University of Technology, Netherlands
		^2Philips Research Eindhoven
		^3University of Rome "La Sapienza"
		5 GHz Low-Noise Bipolar and CMOS Monolithic VCOs
		Jacquinot Helene, Majos Jacques, Senn Patrice
		France Telecom R&D, Meylan, France
		A Fully Integrated Sub-1 V 4 GHz CMOS VCO, and a 10.5 GHz Oscillator
		Ahmed Mostafa, Mourad El-Gamal
		McGill University, Montreal, Canada
		Dynamically Programmable Parallel Processor(DPAA): A Novel Reconfigurable Architecture with Simple Program Interface
		Boon-Keat Tan^1, Ryuji Yoshimura^2, Toshimasa Matsuoka^2, Kenji Taniguchi^2
		^1Osaka Univeristy, Japan
		^2Osaka University
		Transition Pattern Coding: An approach to reduce Energy in Interconnect
		Paul Sotiriadis, Alice Wang, Anantha Chandrakasan
		Massachusetts Institute of Technology, Cambridge MA, United States
		Accurate A Priori Signal Integrity Estimation Using A Multilevel Dynamic Interconnect Model for Deep Submicron VLSI Design
		Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
		Royal Institute of Technology, Kista-Stockholm, Sweden
		Investigation of Cell Leakage and Data Retention in eDRAM
		Masashi Hashimoto^1, Robert Baumann^2
		^1Cadence Design Systems, Japan, Yokohama, Japan
		^2Texas Instruments
		Source-Pulsed Dynamic-Threshold CMOS SRAMs for Fast, Portable Applications
		Azeez Bhavnagarwala^1, Ashok Kapoor^2, James Meindl^1
		^1Georgia Institute of Technology, Atlanta, United States
		^2LSI Logic Corporation
		A Low-Power SRAM with Resonantly Powered Data, Address, Word, and Bit Lines
		Nestoras Tzartzanis^1, William Athas^2, Lars Svensson^3
		^1USC - Information Sciences Institute
		^2House Ear Institute, Los Angeles, United States
		^3SwitchCore
		Super-Compact Shared-Cache Memories with Low Power Consumption for Multi-Issue Single Chip Processors
		Koji Kishi, Takayuki Gyohten, Jongshik Kim, Hans Jürgen Mattausch, Yoshiyuki Tatsumi, Shinji Nara
		Hiroshima University, Higashi-Hiroshima, Japan
		Nonvolatile CMOS Latch Employing GMR Resistors
		Bodhisattva Das^1, Kae Ann Wong^2, William C. Black^1
		^1Iowa State University, Ames, Iowa, USA., United States
		^2Texas Instruments Inc., Dallas, Texas, USA.
		Dynamic Flip-Flop with Improved Power
		Nikola Nedovic, Vojin Oklobdzija
		UC Davis, ECE Department, Davis CA 95616, Berkeley, United States
	20:00	Conference Banquet, until 23:00

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Wednesday, 20 September 2000 Room B

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Session 2.4:

Linear Receiver Circuits

	Chairman: Sven Mattisson
	Ericsson Mobile Communication AB, Lund, Sweden
09:20	A High IP3 RF Receiver Chip Set for Mobile Radio Base Stations up to 2 GHz
	Hans-Dieter Wohlmuth, Werner Simbürger
	Infineon Technologies AG, Munich, Germany
09:45	High Performance SiGe Upconverter for Double Conversion Tuner
	Mehmet Ipek^1, Martin Rieger^2, Heinrich Schemmann^1
	^1THOMSON multimedia, Villingen-Schwenningen, Germany
	^2Univ. of Appl. Sci. Albstadt-Sigmaringen
10:10	Coffee Break, until 10:40

Session 2.5:

Low Power ADCs 1

	Chairman: Peter J. Mole
	Nortel Networks, Harlow, United Kingdom
11:30	1.0-Volt, 9-bit Pipelined CMOS ADC
	Mikko Waltari, Kari Halonen
	Helsinki University of Technology, HUT, Finland
11:55	A Low-Power 14-b 5 MS/s CMOS Pipeline ADC with Background Analog Self-Calibration
	João Goes^1, João Goes^1, João Vital^1, Luis Alves^2, Nuno Ferreira^2, Pedro Ventura^2, Elmar Bach^3, José Franca^1, Rudolf Koch^3
	^1Departamento de Eng. Electrotécnica, Caparica, Portugal
	^2
	^3Infineon
12:20	Lunch Break, until 14:00

Session 2.6:

Low Power ADCs 2

	Chairman: Olivier Nys
	Xemics SA, Neuchatel, Switzerland
14:50	12 Bit Low Power Fully Differential Switched Capacitor Non-Calibrating Successive Approximation ADC with 1MS/s
	Gilbert Promitzer
	Austria Mikro Systeme International AG, Graz, Austria
15:15	An 8-bit 13-Msamples/s Digital-Background-Calibrated Algorithmic ADC
	Eric B. Blecker^1, Ozan E. Erdogan^2, Paul J. Hurst^1, Stephen H. Lewis^1
	^1University of California, Davis, Davis, CA, United States
	^2C-Cube Microsystems Inc
15:40	Coffee Break, until 16:00

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Wednesday, 20 September 2000 Room C

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Session 2.7:

Memory Circuits

	Chairman: Jari Nurmi
	Tampere University of Technology, Finland
09:20	A Dual-Phase-Controlled Dynamic Latched (DDL) Amplifier for High-Speed and Low-Power DRAMs
	Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura, Kazuhiko Kajigaya
	Device Development Center, Hitachi Ltd., Tokyo, Japan
09:45	A High-Efficiency Back-Bias Generator with Cross-Coupled Hybrid Pumping Circuit for sub-1.5 V DRAM applications
	Kyeong-Sik Min, Kyo-Won Jin, Ji-Beom Kim
	Hyundai Electronics Industries Co., Ltd., Cheongju-Si, Korea (South)
10:10	Coffee Break, until 10:40

Session 2.8:

Memories

	Chairman: Jari Nurmi
	Tampere University of Technology, Finland
11:30	A Low Power Reconfigurable I/O DRAM Macro with Single Bit line Writing Scheme
	Jeonghoon Kook, Hoi-Jun Yoo
	Dept. of EECS, KAIST, Korea, Taejon, Korea (South)
11:55	A 1-V, 3.44ns, 4.1-mW at 50-MHz, 128-Kb Four-Way Set-Associative CMOS Cache Memory Implemented by 1.8V 0.18um Foundry CMOS Technology for Low-Voltage Low-Power VLSI System Applications
	James Kuo^1, P. F. Lin^1, F. Wang^2, H. H. Chang^2, W. T. Wang^2, C. H. Chen^2
	^1National Taiwan University, Taipei, Taiwan
	^2TSMC
12:20	Lunch Break, until 14:00

Session 2.9:

Fully Integrated Synthesizers

	Chairman: Franz Dielacher
	Infineon Technologies AG, Villach, Austria
14:50	A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Wireless Receivers
	William Shing-Tak Yan, Howard Luong
	Hong Kong University of Science & Technology, Kowloon, Hong Kong
15:15	Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise
	Patrik Larsson
	Bell Labs, Lucent Technologies, Holmdel, United States
15:40	Coffee Break, until 16:00

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Thursday, 21 September 2000 Room A

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08:30	Future Trends in Automotive Electronics, Sensors and Communication Systems (Invited Paper)
	K.-T. Neumann
	Volkswagen AG, Germany
09:20	ESSCIRC 2001, until 09:25

Session 3.1:

Optical Receivers

	Chairman: Bram Nauta
	University of Twente, Enschede, The Netherlands
09:25	A Receiver Channel with a Leading Edge Timing Discriminator for a Pulsed Time-of-Flight Laser Radar
	Tero Peltola, Tarmo Ruotsalainen, Pasi Palojärvi, Juha Kostamovaara
	University of Oulu, Finland
09:50	A packaged low-noise high-speed regulated cascode transimpedance amplifier using 0.6um N-well CMOS technology
	Sung Min Park^1, Christofer Toumazou^2
	^1Department of EE Engineering, Imperial College, London, United Kingdom
	^2Dept. of EE Eng., Imperial College
10:15	Coffee Break, until 10:45
10:45	VDSL, From Concept to Chips (Invited Paper)
	P. Spruyt
	Alcatel Research, Belgium

Session 3.2:

Integrated Smart Sensors

	Chairman: Werner Brockherde
	Fraunhofer IMS, Duisburg, Germany
11:35	SC Interface and Calibration Circuit for a CMOS Humidity Sensor
	Yanyan Qiu, KongPang PUN, Carlos Azeredo Leme, José Franca
	Instituto Superior Técnico, Lisboa, Portugal
12:00	A Position Detection Sensor for 3-D measurement
	Tomohiro Nezuka^1, Masashi Hoshino^2, Makoto Ikeda^3, Kunihiro Asada^3
	^1University of Tokyo, Japan
	^2Matsushita Electrical Industrial Co. Ltd.
	^3VLSI Design and Education Center
12:25	Lunch Break, until 14:00
14:00	3-D ICs: Motivation, Performance Analysis and Technology (Invited Paper)
	K. Saraswat
	Stanford University, United States

Session 3.3:

Logic Circuit Techniques

	Chairman: Tobias G. Noll
	RWTH Aachen, Germany
14:50	A Skew-Tolerant Design Scheme for Over 1-GHz LSIs
	Yasuhiko Hagihara^1, Shigeto Inui^1, Atsushi Yoshikawa^1, Takahiko Uesugi^2, Takashi Osada^2, Satoshi Nakazato^1, Masashi Ikeda^1, Makoto Okada^1, Shitaka Yamada^1
	^1NEC Corporation, Sagamihara, Japan
	^2NEC Kofu, Ltd.
15:15	A Novel High Speed Low Power Logic Family: Race Logic
	Se Joong Lee, Hoi Jun Yoo
	Dept. of EECS, KAIST, Taejon, Korea (South)
15:40	Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family
	Alexandre Solomatnikov^1, Dinesh Somasekhar^2, Kaushik Roy^1
	^1Department of ECE, Purdue University, West Lafayette, IN, United States
	^2Circuits Research Laboratory, Intel Corp.
16:05	Young Scientists Award & Closing Session, until 16:30

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Thursday, 21 September 2000 Room B

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Session 3.4:

Medical Sensor Systems

	Chairman: Johan H. Huijsing
	Delft University of Technology, The Netherlands
09:25	A Programmable Intraocular CMOS Pressure Sensor System Implant
	K. Stangel, S. Kolnsberg, D. Hammerschmidt, B.J. Hosticka, H.K. Trieu, W. Mokwa
	Fraunhofer Institute of Microelectronic Circuits and Systems, Duisburg, Germany
09:50	A low-power ASK demodulator for inductively coupled implant able electronic
	Gunnar Gudnason
	Dept of IT, Technical University of Denmark, Lyngby, Denmark
10:15	Coffee Break, until 10:45

Session 3.5:

High Speed Data Convertors

	Chairman: Klaas Bult
	Broadcom Netherlands B.V., Bunnik, The Netherlands
11:35	A 1.8V 20mW 1mm2 14b 100MSample/s CMOS DAC
	Mika Petri Tiilikainen
	Nokia Mobile Phones, Helsinki, Finland, Finland
12:00	A 10-bit 200 MS/s CMOS Parallel Pipeline A/D Converter
	Lauri Sumanen, Mikko Waltari, Kari Halonen
	Helsinki University of Technology/ECDL, HUT, Finland
12:25	Lunch Break, until 14:00

Session 3.6:

VCO Circuits

	Chairman: Michiel Steyaert
	ESAT MICAS, Heverlee, Belgium
14:50	A differentially tuned 1.73-1.99GHz Quadrature CMOS VCO for DECT, DCS1800 and GSM with a phasenoise over tuning range between -128dbC/Hz and -137dBc/Hz at 600kHz offset
	Marc J. G. Tiebout
	Infineon Technologies AG, Department Wireless, Munich, Germany
15:15	A Comparison of MOS Varactors in Fully-Integrated CMOS LC VCO's at 5 and 7 GHz
	Herschel Ainspan, Jean-Olivier Plouchart
	IBM T.J. Watson Research Center, NY USA, Yorktown Heights, NY, United States

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Thursday, 21 September 2000 Room C

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Session 3.7:

Modem ASICs

	Chairman: Jos Huisken
	Philips Research Laboratories, Eindhoven, The Netherlands
09:25	A Low-Voltage Low-Power 0.25mm CMOS ADSL Analog Front-End IC
	R. Kokozinski, M. Bresch, D. Hammerschmidt, M. Hesener, B. Hosticky
	Fraunhofer-Institut IMS, Duisburg, Germany
09:50	A Mixed-Signal CMOS MODEM ASIC for Data Transmission on the Low-Voltage
	A. Rodríguez-Vázquez^1, R. Domínguez-Castro^1, M. Delgado-Restituto^1, G. Liñán^1, R. del Río^2, J. Ceballos^2, A. Acosta^2, J. Ramos^2
	^1Instituto de Microelectronica de Sevilla-CNM/CSIC, Spain
	^2stituto de Microelectronica de Sevilla-CNM/CSIC
10:15	Coffee Break, until 10:45

Session 3.8:

High Speed Interfaces

	Chairman: Patrice Senn
	France Telecom / CNET, Meylan Cedex, France
11:35	LVDS I/O Cells with Rail-to-Rail Receiver Input for SONET/SDH at 1.25Gb/s
	Uwe Vogel^1, Rolf Jähne^1, Steffen Ulbricht^1, Gerd Bunk^1, Marcel Steinert^2, Christoph Zimmermann^2, Takeshi Iwamoto^2, Rainer Kokozinski^1
	^1Fraunhofer Institute for Microelectronic Circuits, Dresden, Germany
	^2Toshiba Electronics Europe
12:00	A 10 Gb/s, 120/60 mA Laser/Modulator Driver IC with Dual-mode Actively Matched Output Buffer
	Hans Ransijn, Greg Salvador, Dwight Daugherty, Ken Gaynor
	Lucent Technologies, Reading, United States
12:25	Lunch Break, until 14:00

Session 3.9:

Digital PLL Realisations

	Chairman: Patrick Larsson
	Bell Laboratories, Holmdel, NJ, United States
14:50	New Fast-Lock PLL for mobile GSM GPRS applications
	Bernd Memmler^1, Edmund Goetz^1, Guenther Schoenleber^2
	^1Infineon Technologies, Munich, Germany
	^2GME, Munich
15:15	A 2 GHz Delta-Sigma Fractional-N Frequency Synthesizer in 0.35um CMOS
	Rami Ahola, Kari Halonen
	Helsinki University of Technology, Espoo, Finland
15:40	An Analogue Delay Line for Virtual Clock Enhancement in DDS
	Raik Richter, Hans-Joachim Jentschel
	TU Dresden, Germany