Wednesday 04.10.2000
| Chairmen: | Chairman: E.Langer (AMD, Dresden, Germany) |
| P1 | Faster Fault Isolation Using a Dichotomy
Reduction of Node Candidates R. Desplats, G. Rolland, P. Perdu (CNES- French Space Agency, Toulouse, France) |
| P2 | New Non-Destructive Laser Ablation Based
Backside Sample Preparation Method F. Beaudoin, D. Lewis, F. Salin, F. Saviot, P. Perdu (IXL, Université Bordeaux 1, Talence, France) |
| P3 | A Review of Sample Backside Preparation
Techniques for VLSI P. Perdu, R. Desplats, F. Beaudoin (CNES, Toulouse, France) |
| P4 | A Multifunctional Laser Linking and
Cutting Structure Ole Mende, Dirk Niggemeyer (Laboratorium für Informationstechnologie Universität Hannover, Germany) |
| P5 | Reliability and stability of GaAs-based
pseudomorphic quantum wells for high-precision power metering Y. Haddab, V. Mosser, F. Kobbi, R. Pond (Montrouge Technology Center, Schlumberger Industries, France) |
| P6 | A Method For HBT Process Control and
Defect Detection using Pulsed Electrical Stress C. Sydlo, B. Mottet, M. Schüßler, M. Brandt, H.L. Hartnagel (Inst. für Hochfrequenztechnik, TU-Darmstadt, Germany) |
| P7 | Electrochemical Wet Etching in KOH: H2O
Solution and Secondary/Ion Image Passive Voltage Contrast as a
Complementary Technique in Failure Analysis Oh Chong Khiam, Bi Jian Hua, Shailesh Redkar (Chartered Semiconductor Manufacturing Ltd, Failure Analysis Laboratory, Singapore) |
| P8 | Effects of Test Sequences on Degradation
Analysis in High Speed Connectors M. Catelani, M. Mugnaini, R. Singuaroli, A. Falciani (Department of Electronic and Telecommunications Università di Firenze, Italy) |
| P9 | Bulk and Surface Degradation Mode in
0.35µm Technology gg-nMOS ESD Protection Devices D. Pogany, K. Esmark, M. Litzenberger, C. Fürböck, H. Gossner, E. Gornik (Institute for Solid State Electronics, University of Technology, Vienna, Austria) |
| P10 | Numerical investigation for a grounded
gate NMOS transistor under electrostatic discharge (ESD) through TLP
method P. Galy, V. Berland, B. Foucher, I. Lombaert-Valot, A. Guilhaume, J.-P. Chante, St. Dufrene, S. Bardy (Pole Universitaire Léonard de Vinci, Paris, France, Aerospatiale CCR, Suresnes Cedex, France, CEGELY INSA Lyon, France, Philips Semiconducteurs Composants, Caen, France) |
| P11 | Dimensional Effects on the Reliability of
Polycrystalline Silicon Thin-Film Transistors H.-W. Zan, Po-S. Shih, C.-Y. Chang, T.-C. Chang (Institute of Electronics, National Chao Tung University, Taiwan) |
| P12 | About Long-Term Effects of Hot-Carrier
Stress on n-MOSFETS Barbara Stadlober (Infineon Technologies Villach AG, Villach, Austria) |
| P13 | Reliability of Passivated Polycrystalline
Silicon Thin Film Transistors D.Z. Peng, P.S. Shih, T.C. Chang, C.Y. Chang (Institute of Electronics, National Chiao Tung University, Taiwan, National Nano Device Laboratory, Taiwan) |
| P14 | The Role of the Spreading Resistance
Profiling in Manufacturing Control and Technology Development J. Lin-Kwang, St. Ramey, J.M. Reynes, B. Hillard, T. Thieme (Motorola Semiconductor Products Sector, Toulouse Cedex, France, Solid State Measurement Inc, Pittsburgh, PA, USA, Solid State Measurements GmbH, Dresden, Germany) |