N. Y. A. SHAMMAS, " Present problems of power module packaging technology", Microelectronics Reliability, Volume 43, Issues 4, pp. 519-527.
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Article : [ART415]

Titre : N. Y. A. SHAMMAS, Present problems of power module packaging technology, Microelectronics Reliability, Volume 43, Issues 4, pp. 519-527.

Cité dans :[REVUE417] Elsevier Science, Microelectronics Reliability, Volume 43, Issue 4, Pages 517-684, April 2003.
Cité dans : [DATA197] Les revues Microelectronics Reliability et Microelectronics Journal, ELSEVIER, décembre 2004.
Auteur : N.Y.A. Shammas

Vers : Bibliographie
Adresse : School of Engineering and Advanced Technology, Staffordshire University, Beaconside, P.O. Box 333, Stafford ST18 0DF, UK
Tel. : +44-01785-353265
Fax. : +44-01785-35355
Source : Microelectronics Reliability
Volume : 43
Issues : 4
Date :
Pages : 519 - 527
Lien : private/SHAMMAS2.pdf - 262 Ko, 9 pages.
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Abstract :
An overview of the problems encountered concerning power module performance and
reliability is given and the main failure mechanisms are discussed. Experimental
and simulation methods for the transient thermal characterisation of
semiconductor packages are presented. An identification procedure that allows
establishing the physical correspondence between the RC cells of the thermal
model and the layers that constitute the electronic package is proposed. The
results of tests on a number of commercial Smartpack® modules provide useful
information about the influence of materials properties and geometry on the step
response. These could be used for package quality control and reliability

Article Outline
1. Introduction
2. Failure mechanisms
2.1. Failure mechanisms relating to the silicon chip
2.2. Oxide defects
2.3. Ion migration
2.4. Current crowding/filamentation
2.5. Back metal delamination
2.6. External impacts
2.7. Operating conditions
2.7.1. Operating temperature
2.7.2. Operating frequency
2.7.3. Short circuit conditions
2.8. The encapsulation
2.8.1. Cracking of wire bond
2.8.2. Partial discharge and insulation failure
2.8.3. Delamination
2.8.4. Solder fatigue
2.8.5. Current sharing
3. Identification procedure
3.1. Description of the samples
3.2. Results and discussion
4. Study of structural degradation
4.1. Simulation model
4.2. Results and discussion
5. Conclusions



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  [1] :  [ART575]  P.E. BAGNOLI, C. CASAROSA, M. CIAMPI, E. DALLAGO, Thermal resistance analysis by induced transient (TRAIT) method for power electronic devices thermal characterization - Part I: Fundamentals and theory, IEEE Transactions on Power Electronics, Vol. 13, N
  [2] :  [ART238]  N. Y. A. SHAMMAS, M. P. RODRIGUEZ, F. MASANA, A simple method for evaluating the transient thermal response of semiconductor devices, Microelectronics Reliability, Volume 42, Issues 1, January 2002, pp. 109-117.

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