ESREF'2000, "11th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis", Dresden, Germany, 2-6 octobre 2000.
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Titre : ESREF'2000, 11th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Dresden, Germany, 2-6 octobre 2000.

Cité dans : [CONF016] ESREF, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis et Microelectronics and Reliability, décembre 2005.
Cité dans : [DIV003]  Liste des actes de congrès par années, février 2003.
Cité dans : [DATA197] Les revues Microelectronics Reliability et Microelectronics Journal, ELSEVIER, décembre 2004.
Cité dans :[SHEET459]
Cité dans :[SHEET348]
Cité dans :[SHEET449]
Editors : N.D. Stojadinovic & M.G. Pecht
Editors : L.J. Balk - W.H. Gerling - E. Wolfgang

Résumé : 10 mars 2000 (résumé de 3 pages).
Notification : 10 mai 2000
Final_Paper : 10 juin 2000
Date : 02-06 octobre 2000

Lien : esref/2000/default.htm
Lien : esref/2000/esref2k.pdf - 34 Kb, Call for paper.
Web : http://www.electronics.uni-wupertal.de/ESREF2000
Info : http://cops.cinetic.de/VDE/Fachtagungen/

Vers : Mardi 3 octobre 2000
Vers : Statistiques
Vers : liste des références cited
Vers : Mercredi 4 octobre 2000
Vers : Softwares
Vers : Jeudi 5 octobre 2000
Vers : Vendredi 6 octobre 2000
Info : une copie des transparents des tutoriaux est stockée chez Thierry LEQUEU [DATA126]
Vers : Tutorial 1
Vers : Tutorial 2
Vers : Tutorial 3
Vers : Tutorial 4
Vers : Tutorial 5
Vers : Tutorial 6

  [1] :  [PAP243]  J. LIN-KWANG, S. RAMEY, J.M. REYNES, R.J. HILLARD, T. THIEME, The role of spreading resistance profiling in manufacturing control and technology development, ESREF'2000.


Mardi 3 octobre 2000

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Editors-in-chief : M.G. Pecht
  [1] :  [DATA152] Recherche sur l'auteur M. PECHT, octobre 2002.
c.f copyright et photocopie / norme de rédaction : IZO Z39-1992.
  [1] : [99DIV041] Liste des normes de l'AFNOR, l'U.T.E., de l'ISO, de l'UIC, normes CEM, VDE et MIL STD, septembre 2008.

From IXL : W. Clayes Bordeaux France

  [1] : [SHEET379] S. DILHAIRE, S. JOREZ, A. CORNET, E. SCHAUB, W. CLAEYS, Optical method for the measurement of the thermomechanical behavior of electronic devices, Microelectronics Reliability, no. 39, 1999, pp. 981-985.
  [2] : [SHEET460] S. Dilhaire, S. Jorez, A. Cornet, L.D. Patiño Lopez, W. Claeys, Measurement of the thermomechanical strain of electronic devices by shearography
  [3] :  [DATA147] IXL, Laboratoire IXL, Université de Bordeaux, Talence, France, http://www.ixl.u-bordeaux.fr
Pages_1371-1375 : papier de l'IXL
"Laser cross section measurement for the evaluation of single-event effects in integrated circuits"
V. Pouget, P. Fouillat, D. Lewis, H. Lapuyade, F. Darracq, A. Touboul
  [1] :  [PAP179]  V. POUGET, P. FOUILLAT, D. LEWIS, H. LAPUYADE, F. DARRACQ, A. TOUBOUL, Laser cross section measurement for the evaluation of single-event effects in integrated circuits, ESREF'2000, pp. 1371-1375.

Pages_1727-1731 : papier de l'IXL
"Comparison of RF and DC life-test effects on GaAs power MESFETs"
B. Lambert, N. Saysset-Malbert, N. Labat, F. Verdier, A. Touboul, P. Huguet, F. Garat,

Pages_1425-1429 : papier de l'IXL
"New Non-Destructive Laser Ablation Based Backside Sample Preparation Method"
F. Beaudoin, F. Saviot, D. Lewis, P. Perdu, F. Salin

Pages_1509-1514 : France/Belgique Claeys Bordeaux : Mesure of the strain / CPMOH de Bordeaux
"Measurement of the thermomechanical strain of electronic devices by shearography"
S. Dilhaire, S. Jorez, A. Cornet, L.D. Patiño Lopez, W. Claeys
Info : mesure de déformation par shift phase lazer.

  [1] : [SHEET460] S. Dilhaire, S. Jorez, A. Cornet, L.D. Patiño Lopez, W. Claeys, Measurement of the thermomechanical strain of electronic devices by shearography

Page 5 du programme : F. Jensen, O. Bonnaud de Rennes et E. Vincent ST Microelectronics ?

  [1] : [LIVRE207] F. JENSEN, Electronic Component Reliability, Fundamentals, Modelling, Evaluation, and Assurance, 1995, Chichester, Editions John Wiley & Sons.
  [2] :  [DATA197] Les revues Microelectronics Reliability et Microelectronics Journal, ELSEVIER, décembre 2004.


Statistiques

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23 papiers d'Allemagne, 21 papiers de France, 7 papiers d'Italy +... au total : 85 papiers de 5 pages (environ).
199 participants on the list.
environ 50-100 participants par sessions.

Pages_1305-1309 : TDDB tests pour Slimane.
"Assessment of copper contamination impact on inter-level dielectric reliability performed with time-dependent-dielectric-breakdown tests"
R. Gonella, P. Motte, J. Torres

Page_1365-1370 : ISE + thermal + laser
"Thermal and free carrier concentration mapping during ESD event in Smart Power ESD protection devices using an improved laser interferometric technique"
C. Fürböck, K. Esmark,
Info : M. Litzenberger
D. Pogany, G. Groos, R. Zelsacher, M. Stecher and E. Gornik.

  [1] : [SHEET462] C. FURBOCK, K. ESMARK, M. LITZENBERGER, D. POGANY, G. GROOS, R. ZELSACHER, M. STECHER, E. GORNIK, Thermal and free carrier concentration mapping during ESD event in Smart Power ESD protection devices using an improved laser interferometric technique, ER

Pages_1413-1418 : EBIC et IBIC pour thyristor power device
"Analysis of high-power devices using proton beam induced currents"
M. Zmeck, T. Osipowicz, F. Watt, F. Niedernostheide, H.-J. Schulze, G.B.M. Fiege, L. Balk

  [1] : [SHEET463] M. Zmeck, T. Osipowicz, F. Watt, F. Niedernostheide, H.-J. Schulze, G.B.M. Fiege, L. Balk, Analysis of high-power devices using proton beam induced currents


liste des références cited

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ISPSD'99, ISPSD'2000, IRPS, Microelectronics & Reliability, ECTC, IEEE trans. on Comp. Pack. Manu. Tech.
ESSDERC, IEEE trans on Electron Device, (MRS), IEDM, (IPFA), ESREF'98 et ESREF'99 (surtout les français...)
(ISTFA), (IEEE trans on Comp.), (JAP), (Appl. Phys. Let.), (ECTC).


Mercredi 4 octobre 2000

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Pages_1353-1358 : PICA imaging, back side, 50 um, 1 um d'état de surface, light emission of the current commutation.
"PICA: Backside failure analysis of CMOS circuits using Picosecond Imaging Circuit Analysis"
M.K. Mc Manus, J.A. Kash, S.E. Steen, S. Polonsky, J.C. Tsang, D.R. Knebel, W. Huott
  [1] : [SHEET464] M.K. Mc Manus, J.A. Kash, S.E. Steen, S. Polonsky, J.C. Tsang, D.R. Knebel, W. Huott, PICA: Backside failure analysis of CMOS circuits using Picosecond Imaging Circuit Analysis

Pages_1473-1477 : un article de Chante : thermal simulation Avant! Davinci
"Numerical investigation for a grounded gate NMOS transistor under electrostatic discharge (ESD) through TLP method"
P. GALY, V. BERLAND, B. FOUCHER, I. LOMBAERT-VALOT, A. GUILHAUME, J.P. CHANTE, S. DUFRENNE, S. BARDY.


Softwares

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ISE, AVANT!, SUPREM, MEDICI, ANSYS.

Pages_1521-1526 : Al wire bons ISPSD'2000 ?? (cf SHEET396) Coffin-Manson Law
"Reliability Model for Al Wire Bonds subjected to Heel Crack Failures"
S. Ramminger, N.Seliger, G.Wachutka
[1] V. Mehrotra: "Wirebond Reliability in IGBT-Power Modules: Application of High Resolution Strain and Temperature Mapping", Proc. ISPSD’99, pp. 113-116, 1999

  [1] : [SHEET465] S. RAMMINGER, N. SELIGER, G. WACHUTKA, Reliability Model for Al Wire Bonds subjected to Heel Crack Failures, ESREF'2000, pp. 1521-1526.
  [2] : [99ART111] MEHROTRA V., HE J., DADKHAH M.S., RUGG K., SHAW M.C., Wirebond reliability in IGBT-Power modules : application of high resolution strain and temperature mapping, ISPSD'99.
  [3] : [SHEET396] C. Hager, A. Stuck, Y. Tronel, R. Zehringer, W. Fichtner, Comparison between Finite-Element and Analytical Calculations for the Lifetime Estimation of Bond Wires in IGBT Modules, ISPSD'2000, pp. 291-294.

Pages_1591-1597 : pour Slimane
"A complementary molecular-model (including field and current) for TDDB in SiO2 dielectrics"
J. W. McPherson, R. B. Khamankar and A. Shanware

Pages_1615-1618 : Vérification de la loi Gaussienne avec "inv CDF cume %" Cumulative Defect Function
"Technique for determining a prudent voltage stress to improve product quality and reliability"
Richard C.Blish,II, J.Courtney Black, Ben Hui, Don T.Prince
[1] P. Tobias and D. Trindade, Applied Reliability (2 nd Edition). Van Nostrand Reinhold, New York, 1995.
[2] Elsayed, Reliability Engineering. Addison Wesley, MA, 1996.

  [1] : [SHEET466] Richard C.Blish,II, J.Courtney Black, Ben Hui, Don T.Prince, Technique for determining a prudent voltage stress to improve product quality and reliability

Pages_1653-1658 : M.H. Poech creep behavior.
"A modelling approach to assess the creep behaviour of large-area solder joints"
M.H. Poech, R. Eisele.
[1] Lau J, Thermal Stress and Strain in Microelectronics Packaging, Van Nostrand Reinhold, New York, 1993

  [1] : [SHEET467] M.H. Poech, R. Eisele, A modelling approach to assess the creep behaviour of large-area solder joints
  [2] : [SHEET146] K.J. DITTMER, M.H. POECH, F.W. WULFF, M. KRUMM, Failure analysis of aluminum wire bonds in high power IGBT modules, Proceedings of the Spring Meeting on MRS, San Francisco, USA, April 1995, pp. 251-256.

Pages_1659-1663 : Reliability testing EUPEC (cf thèse d'Hamidi), IGBT
"Reliability testing of high-power multi-chip IGBT modules"
G. Lefranc, T. Licht, H.J. Schultz, R. Beinert, G. Mitic
Info : des IGBT 6.5 kV pour une utilisation en DC 3.5 kV (coefficient de 2 environ)
up to 2400A ! power dissipation up to 200W/cm2. 100 FIT for traction application : 1 failure in 10e7 heures composants.
Thermocouples diamêtre 2 mm, courant I = 1200 A, P = 4.5 kW.
Pour les soudures : Acoustic Scanning Microscope

  [1] :  [ART183]  G. LEFRANC, T. LICHT, H.J. SCHULTZ, R. BEINERT, G. MITIC, Reliability testing of high-power multi-chip IGBT modules, ESREF'2000, pp. 1659-1663.

Pages_1665-1670 : Coquery Lallemand : 4000 heures IGBT testing
"Failure criteria for long term Accelerated Power Cycling Test linked to electrical turn off SOA on IGBT module. A 4000 hours test on 1200A-3300V module with AlSiC base plate."
G.Coquery, R.Lallemand.
Sur les 13 références : ISPSD'2000, ESREF'98, ESREF'99, EPE'99, PCIM'97, ISTFA'95.
Lien : coquery1.pdf - 423 Ko, 6 pages

  [1] : [SHEET516] G. COQUERY, R. LALLEMAND, Failure criteria for long term Accelerated Power Cycling Test linked to electrical turn off SOA on IGBT module. A 4000 hours test on 1200A-3300V module with AlSiC base plate, ESREF'2000, pp. 1665-1670.

Pages_1679-1682 : Reliability of Power MOSFET TDDB at 175°C, 200°C, 225°C (oxyde).
"Reliability aspects of high temperature power MOSFETs"
J.V. Manca, W. Wondrak, W. Schaper, K. Croes, J. D’Haen, W. De Ceuninck, B. Dieval, H.L. Hartnagel, M. D’Olieslaeger and L. De Schepper.

  [1] :  [PAP432]  J.V. MANCA, W. WONDRAK, W. SCHAPER, K. CROES, J. D’HAEN, W. DE CEUNINCK, B. DIEVAL, H.L. HARTNAGEL, M. D’OLIESLAEGER, L. DE SCHEPPER, Reliability aspects of high temperature power MOSFETs, ESREF'2000.

Pages_1701-1708 : Reliability of optoelectronic : somme et produit de "Failure Rate" ?!
"Reliability of optoelectronic components for telecommunications"
D. Sauvage, D. Laffitte, J. Périnet, Ph. Berthier, J.L. Goudard

Pages_1533-1538 : Broek en ref. Also ECTC
"Vertical die crack stresses of Flip Chip induced in major package assembly processes"
D.G. Yang, L.J. Ernst, C. van ‘t Hof, M.S. Kiasat, J. Bisschop, J. Janssen, F. Kuper, Z. N. Liang, R. Schravendeel, G.Q. Zhang
Info : In reference [1], Van Kessel et al determined the fracture toughness of silicon is 25.9 N/mm e(2/3).
[1] Van Kessel, C.G.M, Gee, A.S. and Murphy,J.J., The quality of die-attachment and its relationship to vertical die cracking ,IEEE Trans. Comp., Hybr., Manufac. Tech., vol. 6, no.4 , 1983, pp. 414-420.
[13] Broek, D., Elementary engineering fracture mechanics (4 th edition), Martinus Nijhof Publishers, 1986, pp. 88-94.

  [1] : [SHEET468] D.G. YANG, L.J. ERNST, C. VAN'T HOF, M.S. KIASAT, J. BISSCHOP, J. JANSSEN, F. KUPER, Z. N. LIANG, R. SCHRAVENDEEL, G.Q. ZHANG, Vertical die crack stresses of Flip Chip induced in major package assembly processes, ESREF'2000, pp. 1533-1538.
  [2] : [LIVRE200] D. BROEK, Elementary Engineering Fracture Mechanics, June 1982, Martinus Nijhoff Publishers, 524 pages.

Pages_1539-1543 : Acoustic Micro Imaging Sonoscan Janet E. Semmens
"Flip Chips and Acoustic Micro Imaging: An Overview of Past Applications, Present Status, And Roadmap for the Future"
Janet E. Semmens
Info : cf visit card. résolution 10 um, meilleur en Z, surtout sans le boitier plastique.
Web : http://www.sonoscan.com

  [1] : [SHEET469] Janet E. Semmens, Flip Chips and Acoustic Micro Imaging: An Overview of Past Applications, Present Status, And Roadmap for the Future


Jeudi 5 octobre 2000

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Pages_1721-1726 : Simulation et analiticely approach. Optimize test time. What is moisture (humidité) and yield (rendement) ?
"A method to minimize test time for accelerated ageing of pHEMT’s by analysis of the electronic fingerprint of the initial stage of degradation"
R.Petersen, W. De Ceuninck, L. De Schepper, J.-L. Muraro

Pages_1711 : Arrhenius plot : MTTF = f(1000/Tch) en °C

Pages_1739-1746 : About M. CIAPPA : ESD in CMOS and BCD
"Quantification of Scanning Capacitance Microscopy Measurements for 2D Dopant Profiling"
P. Malberti, L.Ciampolini, M. Ciappa, and W. Fichtner

Pages_1727-1731 : contact Bordeaux
"Comparison of RF and DC life-test effects on GaAs power MESFETs"
B. Lambert, N. Saysset-Malbert, N. Labat, F. Verdier, A. Touboul, P. Huguet, F. Garat
Info : Labat est du IXL, alors que S. Dilhaire est du CPMOH.

Pages_1629-1634 : Calipso: le défaut est trop simplifié. Il ne correspond pas à la réalité des défauts (électromigration).
Les manip "idéales" réalisées correspondent donc bien avec la simulation !
"CALYPSO - Critical Area, Lifetime, and Yield Predicting Software"
P. Miskowiec, D. Kunze, K. Lukat


Vendredi 6 octobre 2000

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Pages_1647-1652 : présentation de C. PICARD du CLOES !
"USE OF ELECTRICAL STRESS AND ISOCHRONAL ANNEALING ON POWER MOSFETS IN ORDER TO CHARACTERIZE THE EFFECTS OF 60 CO IRRADIATION"
C. Picard, C. Brisset, A. Hoffmann, J-P. Charles, F. Joffre, L. Adams, A. Holmes Siedle
[12] L. Lorentz, G. Deboy, A. Knapp, and M. Märtz, "CoolMOS TM a New Millestone in a High Voltage Power MOS"
available on a web site of Infineon http://www.infineon.com ?

  [1] : [SHEET348] S. FORSTER, T. LEQUEU, R. JERISIAN,A. HOFFMANN, 3-D analysis of the breakdown localized defects of ACSTM through a triac study, ESREF'2000, october 2000, pp. 1695-1700.
  [2] : [SHEET449] P.E. NICOLLIAN, W.R. HUNTER, J.C. HU, Experimental Evidence for Voltage Driven Break-down Models in Ultrathin Gate Oxides, IRPS'2000.


Tutorial 1

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Date : Monday Oct. 2, 14:00 - 16:00 h, Room 3
Planning and Performing Accelerated Testing of Microelec-tronic Devices, Traditional and New Methods.
L. Rimestad, Dept. Appl. Electronics, Danish Techn. University, Lingby
This tutorial aims at giving an overview of some of the most viable
methods for accelerated testing of microelectronic devices.
The design of the test and the allocation of test specimens is
important for the succes of the experiment. Damage accumula-tion,
wear-out test methods and extrapolation to give a life esti-mate
will be demonstrated together with the relationsship plotting
techniques designed for this.
Also, the alternative robustness testing and random overload
methods will be shown. Furthermore, a few examples of analysis
of failure patterns, also for censored data will be given.


Tutorial 2

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Date : Monday Oct. 2, 16:30 - 18:30 h, Room 3
Qualification for Reliability in Time-to-Market Driven Product Creation Processes. An intercompany project *)
F. Wulfert, Motorola, Germany, H. Tiemeyer, Infineon Technologies, Germany
The penetration of semiconductor products into the variety of
application segments together with their economic forces of cost.12
and time-to-market enforce more efficient qualification concepts.
This influences the organisation of the qualifcation process in rela-tion
to the development / innovation process as well as the choice
of qualification concepts.
The practices of qualifying products for reliability are changing from
traditional stress testing with qualitative relationships to use condi-tions
to procedures which are more strictly related to the physics
of failure at an improved quantitative level. This also provides the
basis for adaption to specifc application segments.
Based on the project work by experts of a group of semiconductor
companies, the tutorial will give the principles of the different con-cepts,
discuss the transition and introduce into a systematic pro-cedure
for identication of those aspects, which need to be quali-fied,
by making best use of existing knowledge (available results).
As a result, qualification is integrated into the development pro-cess
for improvement of time to market.
*) J. Bisschop 1) , H. Brunner 2) , W. Gerling 2) , G. Kolmeder 3) ,
B. Lange 4) , H. K. Min 5) , A. Preussger 2) , F. Speroni 6) , H. Tiemeyer 2) ,
J. O. Weidner 7) , F. Wulfert 8)
1) Philips, Nijmegen;
2) Infineon Technologies, Munich;
3) Hitachi, Landshut;
4) Texas Instruments, Freising;
5) National Semiconductors, Santa Clara;
6) ST Microelectronics, Milano;
7) AMD, Dresden;
8) Motorola, Munich


Tutorial 3

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Date : Tuesday Oct. 3, 8:00 - 10:00 h, Room 2
Non-Volatile Memory Reliability
J. Van Houdt, IMEC, Belgium
Nonvolatile memories based on the floating gate storage principle
have recently emerged into a large volume market tracing DRAM
in terms of density (currently 256-512Mbit) and cost per Mega-byte.
This is entirely due to the booming Flash memory market
which is triggered not only by the unique properties of Flash, but
also by entirely new applications for stand-alone as well as for
embedded memories.
In the case of state-of-the-art stand-alone memories, the huge
(Gigabit-level) density requires outstanding reliability features. But
also in the embedded case, robustness is of utmost importance
since complicated ECC and verify schemes are undesirable due to
their larger relative overhead in terms of silicon estate as com-pared
to stand-alonememories.
This tutorial will, therefore, focus on the major reliability issues of
Floating Gate memory, addressing however also a number of typi-cal
Flash-related problems. After reviewing the physics of the
major program and erase mechanisms, the respective reliability
issues and the associated physics will be discussed as well as
generic solutions. This includes write/erase endurance, the over-erase
issue, high and low temperature charge retention behaviour,
disturb phenomena during programming, erasing and read-out,
soft-write effects and Stress-Induced Leakage Currents..13


Tutorial 4

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Date : Tuesday Oct. 3, 8:00 - 10:00 h, Room 3
The Work of the GOOD-DIE II Network of Excellence in Europe on the Infrastructure for Semiconductor Technologies
J. Roggen, IMEC, Belgium, M. Roughton, MGR Consultants and D. Radley, Fretwell-Downing Facilities, Great Britain
The GOOD-DIE Network of Excellence was formed in November
with the objective of collecting and disseminating information on
various aspects of bare die, flip chip and CSP technologies
through the means of newsletters, seminars, conferences and a
web site. The partners involved in generating this information are
Philips (CH), IMEC (B), Eltek (UK), Rood (UK), Fretwell-Downing
(UK), Alcatel (B), Infineon (D) and MCC (USA).
This tutorial will cover the general areas of technology that the
group are studying which covers road-mapping, test strategies,
handling and delivery methods, training requirements, CAD/CAM
interfaces and the role of microsystems using bare die.
Also a more detailed presentation will be given on the generation
of a standard for procuring bare die, flip chip and CSP covering
such topics as mechanical, quality, handling, thermal and electrical
simulation for the procurements of such components, particular
requirements for types of die such as bare die, TAB, flip chip, CSP
etc. and the generation of a data exchange format and dictionary.


Tutorial 5

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Date : Tuesday Oct. 3, 10:30 - 12:30 h, Room 2
Using the Internet to obtain Quality and Reliability Information
R. Thomas, Technology Expert Network, USA
H. Livingston, Independent Researcher, USA
The tutorial will briefly cover the basic operation of the internet,
how to access and optimize the use of browsers to view, down-load
and store information.
The major portion of the tutorial will be directed towards accessing
quality and reliability information that is available on the internet.
This will begin with the use of search engines to locate informa-tion,
live and recorded demonstrations of all the known internet
sources that might be of interest to ESREF attendees. These
would include professional sites like IEEE Opera, Computer
Industry Quality Council, NASA, ESA, JPL, University sites, com-mercial
quality and reliability data bases, and conference sites.
Other topics, such as people finders, and effective use of email for
correspondence will be covered if time permits.
A complete set of notes and screen camera recordings will be
available in pdf format on a CD to be handed out to all attendees
at the symposium.


Tutorial 6

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Date : Tuesday Oct. 3, 10:30 - 12:30 h, Room 3
Application of Electron Beam Probing for Design Verifcation and Failure Analysis
S. Goerlich, Infineon Technologies, Germany
Electron beam probing has become an indispensable tool for IC-internal
debugging of microelectronic devices for both design veri-fication
and failure analysis. This tutorial will start with the physical
basics of voltage contrast and quantitative voltage measurement,
discuss the problems of charging and radiation damage, and
describe the useful areas of capacitive coupling voltage contrast.
Technical principle of the modern e-beam probers will be outlined.
In the section about practical application the necessary integration
with CAD and CAT will be stressed: design for analyses, CAD-navigation,
and hardware integration with verification tester. Prac-tical
aspects for the typical debugging flow are choice of packag-ing,
realization of test loops and preparation of probing pads with
focused ion beam. Examples for both design verification and fail-ure
analysis at different kind of integrated circuits will be given, e.g.
DRAMs, micro-controllers and consumer electronics.


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